P89C538 データシートの表示（PDF） - Philips Electronics

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P89C538

CMOS single-chip 8-bit microcontrollers with FLASH program memory

Philips Electronics 

Philips Semiconductors

CMOS single-chip 8-bit microcontrollers

with FLASH program memory

Preliminary specification

89C535/89C536/89C538

Interrupt Priority Structure

The 89C535/536/538 has a 6-source two-level interrupt structure

(see Table 7). There are 2 SFRs associated with the interrupts on

the 89C535/536/538. They are the IE and IP. (See Figures 6 and 7.)

The function of the IPH SFR is simple and when combined with the

IP SFR determines the priority of each interrupt. The priority of each

interrupt is determined as shown in the following table:

PRIORITY BITS

IP.x

INTERRUPT PRIORITY LEVEL

0

Level 0 (lowest priority)

1

Level 1 (highest priority)

An interrupt will be serviced as long as an interrupt of equal or

higher priority is not already being serviced. If an interrupt of equal

or higher level priority is being serviced, the new interrupt will wait

until it is finished before being serviced. If a lower priority level

interrupt is being serviced, it will be stopped and the new interrupt

serviced. When the new interrupt is finished, the lower priority level

interrupt that was stopped will be completed.

Table 7. Interrupt Table

SOURCE

POLLING PRIORITY

X0

1

T0

2

X1

3

T1

4

SP

5

T2

6

NOTES:

1. L = Level activated

2. T = Transition activated

REQUEST BITS

IE0

TP0

IE1

TF1

R1, TI

TF2, EXF2

HARDWARE CLEAR?

N (L)1 Y (T)2

Y

N (L) Y (T)

Y

N

N

VECTOR ADDRESS

03H

0BH

13H

1BH

23H

2BH

1997 Jun 05

13

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