P89C538 データシートの表示（PDF） - Philips Electronics

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P89C538

CMOS single-chip 8-bit microcontrollers with FLASH program memory

Philips Electronics 

Philips Semiconductors

CMOS single-chip 8-bit microcontrollers

with FLASH program memory

Preliminary specification

89C535/89C536/89C538

DC ELECTRICAL CHARACTERISTICS

Tamb = 0°C to +70°C; 5V ±10%; VSS = 0V

SYMBOL

PARAMETER

VIL

Input low voltage

VIH

Input high voltage (ports 0, 1, 2, 3, EA)

VIH1

Input high voltage, XTAL1, RST

VOL

Output low voltage, ports 1, 2, 3 6

VOL1

Output low voltage, port 0, ALE, PSEN 5, 6

VOH

VOH1

IIL

ITL

ILI

ICC

Output high voltage, ports 1, 2, 3 2

Output high voltage (port 0 in external bus mode), ALE7,

PSEN2

Logical 0 input current, ports 1, 2, 3

Logical 1-to-0 transition current, ports 1, 2, 3

Input leakage current, port 0

Power supply current (see Figure 16):

Active mode

Idle mode

Power-down mode or clock stopped

(see Figure 20 for conditions)

TEST

CONDITIONS

4.5V < VCC < 5.5V

VCC = 4.5V

IOL = 1.6mA1

VCC = 4.5V

IOL = 3.2mA1

VCC = 4.5V

IOH = –30µA

VCC = 4.5V

IOH = –800µA

VIN = 0.4V

VIN = 2.0V

See note 3

0.45 < VIN < VCC – 0.3

See note 4

VCC = 5.5V

FREQ = 24 MHz

Tamb = 0°C to 70°C

LIMITS

MIN

MAX

–0.5

0.2VCC+0.9

0.7VCC

0.2VCC–0.1

VCC+0.5

VCC+0.5

0.4

UNIT

V

V

V

V

0.4

V

VCC – 0.7

V

VCC – 0.7

V

–1

–50

µA

–650

µA

±10

µA

60

mA

25

mA

100

µA

RRST

Internal reset pull-down resistor

40

225

kΩ

NOTES:

1. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due

to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the

worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify

ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no

single output sinks more than 5mA and no more than two outputs exceed the test conditions.

2. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VCC–0.7 specification when the

address bits are stabilizing.

3. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its

maximum value when VIN is approximately 2V.

4. See Figures 17 through 20 for ICC test conditions.

Active mode: ICC(MAX) = 0.9 × FREQ. + 1.1mA

Idle mode:

ICC(MAX) = 0.18 × FREQ. +1.0mA; See Figure 16.

5. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.

6. Under steady state (non-transient) conditions, IOL must be externally limited as follows:

Maximum IOL per port pin:

15mA

Maximum IOL per 8-bit port:

26mA

Maximum total IOL for all outputs: 71mA

If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed

test conditions.

7. ALE is tested to VOH1, except when ALE is off then VOH is the voltage specification.

8. Pin capacitance is characterized but not tested. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF

(except EA is 25pF).

1997 Jun 05

17

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