A1442 データシートの表示（PDF） - Allegro MicroSystems

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A1442

Low Voltage Full Bridge Brushless DC Motor Driver with Hall Commutation and Soft Switching, and Reverse Battery, Short Circuit, and Thermal Shutdown Protection

Allegro MicroSystems 

A1442

Low Voltage Full Bridge Brushless DC Motor Driver

with Hall Commutation and Soft Switching,

and Reverse Battery, Short Circuit, and Thermal Shutdown Protection

Power Derating

The device must be operated below the maximum junction tem-

perature of the device, TJ(max). Under certain combinations of

peak conditions, reliable operation may require derating supplied

power or improving the heat dissipation properties of the appli-

cation. This section presents a procedure for correlating factors

affecting operating TJ. (Thermal data is also available on the

Allegro MicroSystems Web site.) The package thermal resistance,

RθJA, is a figure of merit summarizing the ability of the appli-

cation and the device to dissipate heat from the junction (die),

through all paths to the ambient air. Its primary component is the

effective thermal conductivity, K, of the printed circuit board,

including adjacent devices and traces. Radiation from the die

through the device case, RθJC, is relatively small component of

RθJA. Ambient air temperature, TA, and air motion are significant

external factors, damped by overmolding. The effect of varying

power levels (power dissipation, PD) can be estimated. The fol-

lowing formulas represent the fundamental relationships used to

estimate TJ at given levels of PD.

Given:

PD = VIN × IIN ,

(1)

ΔT = PD × RθJA , and

(2)

TJ = TA + ΔT

(3)

For a load of 30 Ω, given common conditions such as: TA= 25°C,

VDD = 3 V, IDD = 83 mA, VL = 2.43 V, IL = 81 mA and RθJA =

250 °C/W, then:

PD = VDD × IDD – VLIL

= 3 V × 83 mA – 2.43 V × 81 mA = 52.17 mW ,

ΔT = PD × RθJA

= 52.17 mW × 250 °C/W = 13°C , and

TJ = TA + ΔT = 25°C + 13°C = 38°C

A worst-case estimate, PD(max), represents the maximum allow-

able power level, without exceeding TJ(max), at a selected RθJA

and TA.

VBATT

System Logic

Control

I/O

IDD

CBYP

0.1 μF

VDD

A1442

SLEEP

VOUT1

VOUT2

NC

GND

IL

M

Figure 4. Typical application showing current paths

Allegro MicroSystems, Inc.

6

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

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