A2550 データシートの表示（PDF） - Allegro MicroSystems

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A2550

Relay Driver with 5 V Regulator for Automotive Applications

Allegro MicroSystems 

A2550

Relay Driver with 5 V Regulator

for Automotive Applications

Timing Diagram: VREG5 UVLO and TSD Monitoring

VBB

VREG5

WDI

CWD

Internal

VREG5 UVLO

CPOR

NPOR

Internal

TSD

OUTx outputs enabled

1

2

VUVREG5

Internal Vref

Internal Vref

~INx

3

4

5

~INx

1. VREG5 undervoltage detected.

2. VREG5 recovers, and after it rises above VUVREG5 + VUVREG5(Hys),

UVLO flag is deactivated and CPOR recharges.

3. NPOR inactive, but outputs not enabled until watchdog detected.

4. TSD event detected and NPOR is activated. When VREG5 ≤ VUVREG5 ,

VREG5 shuts down.

5. TSD flag deactivated (VREG5 allowed to rise; steps 2 and 3 repeat)

Allegro MicroSystems, Inc.

10

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

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