A8287SLB データシートの表示（PDF） - Allegro MicroSystems
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A8287SLB Datasheet PDF : 17 Pages
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A8285/A8287
LNB Supply and Control Voltage Regulator
Bit 5 (ENB). When set to 1, enables the LNB output. When
set to 0, the LNB output is disabled.
Bit 6 (ILIM). Selects the ILIM level. When set to 0, the lower
limit (typically 500 mA) is selected. When set to 1, the
higher limit (typically 700 mA), is selected.
Bit 7 (ENT). When set to 1, enables modulation of the
LNB output with the the internal 22 kHz tone. Since the I2C
interface is compatible with the 400 kHz transfer speed, this
bit may be used to encode DiSEqC™ 2.0 tone bursts for
communication with the LNB or switcher at the far end of
the coaxial cable.
Status Register (I2C Read Register). The main fault
conditions: overcurrent, undervoltage, and overtemperature,
are all indicated by setting the relevant bit in the Status
register. In all fault cases, once the bit is set it is not reset
until the A8285/A8287 is read by the I2C master. The cur-
rent status of the LNB output is also indicated by DIS. DIS
and PNG are the only bits that may be reset without an I2C
read sequence. The normal sequence of the master in a fault
condition is to detect the fault by reading the Status register,
then rereading the Status register until the status bit is reset,
indicating the fault condition has been reset. The fault may
be detected by: continuously polling, responding to an inter-
rupt request (IRQ), or detecting a fault condition externally
and performing a diagnostic poll of all slave devices. Note
that the fully operational condition of the Status register is
all 0s. This simplifies checking of the status byte.
Control (I2C Write) Register Table
Bit Name
Function
0
VSEL0
1
VSEL1 See Output Voltage Amplitude
Selection Table
2
VSEL2
0: LNBx = Low range
3
VSEL3
1: LNBx = High range
0: Overcurrent disable time off
4
ODT
1: Overcurrent disable time on
0: Disable LNB Output
5
ENB
1: Enable LNB Output
0: Overcurrent Limit = 500mA
6
ILIM
1: Overcurrent Limit = 700mA
0: Disable Tone
7
ENT
1: Enable 22KHz internal tone
Bit 0 (TSD). A 1 indicates that the A8285/A8287 has
detected an overtemperature condition and has disabled
the LNB output. DIS is set and the A8285/A8287 does not
re-enable the output until so instructed by writing the rel-
evant bit into the Control register. The status of the overtem-
perature condition is sampled on the rising edge of the ninth
clock pulse in the data read sequence. If the condition is no
longer present, then the TSD bit is reset, allowing the master
to re-enable the LNB output if required. If the condition is
still present, then the TSD bit remains at 1.
Bit 1 (OCP) Overcurrent. If the A8285/A8287 detects an
overcurrent condition for greater than the detection time, and
if ODT is enabled, the LNB output is then disabled. Also, the
OCP bit is set to indicate that an overcurrent has occurred,
and the DIS bit is set. The Status register is updated on the
rising edge of the ninth clock pulse. The OCP bit is reset in
all cases, allowing the master to re-enable the LNB output. If
the overcurrent timer is not enabled, the A8285/A8287 oper-
ates in current limit indefinitely, and the OCP bit is not set.
Bit 2 and 3. Reserved.
Bit 4 (PNG) Power Not Good. Set to 1 when the LNB
output is enabled and the LNB output volts are below 85%
of the programmed LNB voltage. The PNG is reset when the
LNB volts are within 90% of the programmed LNB voltage.
Bit 5 (DIS) LNB output disabled. DIS is used to indicate
the current condition of the LNB output. At power-on, or if
a fault condition occurs, the disable bit is set. Having this bit
change to 1 does not cause the IRQ to activate because the
LNB output may be disabled intentionally by the I2C master.
This bit also is reset at the end of a write sequence, if the
LNB output is enabled.
Bit 6. Reserved.
Bit 7 (VUV) Undervoltage lockout. Set to 1 to indicate that
the A8285/A8287 has detected that the input supply VIN is, or
has been, below the minimum level and that an undervoltage
lockout has occurred, which has disabled the LNB output.
Bit 5 also is set, and the A8285/A8287 does not re-enable the
output until so instructed (by having the relevant bit written
into the Control register). The status of the undervoltage con-
dition is sampled on the rising edge of the ninth clock pulse
in the data read sequence. If the condition is no longer pres-
ent, the VUV bit is reset, allowing the master to re-enable the
LNB output if required. If the condition is still present, the
VUV bit remains set to 1.
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