ACE9030FP2Q データシートの表示（PDF） - Mitel Networks
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ACE9030FP2Q Datasheet PDF : 39 Pages
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ACE9030
PIN DESCRIPTIONS
The relevant supplies (VDD) and grounds (VSS) for each circuit function are listed. All VDD and VSS pins should be used.
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Name
AMPO2
RXCD
LATCHC
LATCHB
DATA
CL
AFCOUT
AUDIO
BP
AFCIN
IREF
VSSL
VDDL
CLK8
C8B
VDDSUB2
CIN2
CIN1
DOUT2
DAC1
DAC2
DOUT8
ADC5
ADC3B
ADC3A
ADC1
LO2
VSSA
VDDA
DOUT1
VDDX
DOUT0
VDDD
RSC
DECOUP
RSMA
PDP
PDI
VSSD
FIM
FIMB
VSSSA
VDDSA
FIA
FIAB
DOUT7
DOUT6
DOUT5
MODMP
MODMN
TEST
PDA
VDDSUB
DOUT3
DOUT4
AMPP2
AMPN2
DAC3
AMPP1
AMPN1
AMPO1
ADC2A
ADC2B
ADC4
Description
LF amplifier 2 output.
Receive carrier detect (ADC1 comparator) output.
Synthesiser programme enable input.
Radio interface programme enable input.
Serial data; programming input, results output.
Clock input for programming bus and for I.F. sampling.
Output from AFC amplifier after sampling.
Output from f.m. discriminator after filtering.
Feedback input to audio bandpass filter.
Input to AFC amplifier and f.m. discriminator.
Bias current input for radio interface, connect setting resistor to ground.
Ground for radio interface logic.
Power supply to radio interface logic.
Output clock at 8·064 MHz, locked to crystal.
8·064 MHz oscillator charge pump output and control voltage input.
Second connection for clean positive supply to bias substrate.
Connection for crystal oscillator.
Connection for crystal oscillator.
Digital control output 2.
Analog control output 1.
Analog control output 2.
Digital control output 8.
Analog to digital converter input 5.
Analog to digital converter input 3B.
Analog to digital converter input 3A.
Analog to digital converter input 1.
Output from crystal frequency multiplier.
Ground for radio interface analog parts.
Power supply to radio interface analog parts.
Digital control output 1.
Power supply to DOUT1 and DOUT2 switches.
Digital control output 0.
Power supply to synthesisers, except input buffers and the bandgap.
Fractional-N compensation bias current, resistor to ground.
Bandgap reference decoupling capacitor connection.
Bias current for synthesiser charge pumps, resistor to ground.
Main synthesiser proportional charge pump output.
Main synthesiser integral charge pump output.
Ground for synthesisers, except input buffers and the bandgap.
Main synthesiser positive input from prescaler.
Main synthesiser negative input from prescaler.
Ground for FIM and FIA input buffers and the bandgap.
Power for FIM and FIA input buffers and the bandgap.
Auxiliary synthesiser positive input from VCO.
Auxiliary synthesiser negative input from VCO.
Digital control output 7.
Digital control output 6.
Digital control output 5.
Modulus control output to prescaler - positive sense.
Modulus control output to prescaler - negative sense.
Test input and output for synthesisers.
Auxiliary synthesiser charge pump output.
Clean positive supply to bias substrate.
Digital control output 3.
Digital control output 4.
LF amplifier 2 positive input.
LF amplifier 2 negative input.
Analog control output 3.
LF amplifier 1 positive input.
LF amplifier 1 negative input.
LF amplifier 1 output.
Analog to digital converter input 2A.
Analog to digital converter input 2B.
Analog to digital converter input 4.
VDD
VDDA
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDA
VDDA
VDDL
–
–
–
VDDL
VDDA
VDDA
VDDL
VDDL
VDDL
VDDA
VDDA
VDDA
VDDA
VDDA
VDDA
VDDA
VDDA
–
–
VDDX
–
VDDX
–
–
VDDSA
–
VDDD
VDDD
–
VDDSA
VDDSA
–
–
VDDSA
VDDSA
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
–
VDDL
VDDL
VDDA
VDDA
VDDL
VDDA
VDDA
VDDA
VDDA
VDDA
VDDA
VSS
VSSA
VSSL
VSSL
VSSL
VSSL
VSSL
VSSL
VSSA
VSSA
VSSL
VSSA
–
–
VSSL
VSSA
VSSA
VSSL
VSSL
VSSL
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
–
–
–
–
–
–
VSSSA
VSSSA
VSSSA
VSSD
VSSD
–
VSSSA
VSSSA
–
–
VSSSA
VSSSA
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
–
VSSL
VSSL
VSSA
VSSA
VSSL
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
3
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