ACE9030M データシートの表示（PDF） - Mitel Networks

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ACE9030M

Radio Interface and Twin Synthesiser

Mitel Networks 

ACE9030

ELECTRICAL CHARACTERISTICS

These characteristics apply over these ranges of conditions (unless otherwise stated):

TAMB = – 40 °C to + 85 °C, all VDD = + 3·6 to + 5·0 V, GND ref. = VSS

A.C. Characteristics (continued)

Parameter

LO2 Multiplier

Amplitude

Reference frequency content of output

2nd, 4th harmonic content of output

5th harmonic of output

6th and higher harmonics in output

SYNTHESISERS

Reference divider

Reference divider input frequency

Drive level into CIN1 from external oscillator

CIN1 input capacitance

CIN1 input resistance

Auxiliary synthesiser

FIA input frequency

Rise and fall times of inputs

Timing Skew between FIA and FIAB

FIA, FIAB differential signal level with both

sides driven

FIA single input drive level with FIAB

decoupled to VSS

FIA, FIAB common mode range

FIA, FIAB common mode range

FIA, FIAB input capacitance

FIA, FIAB differential input resistance

Auxiliary Synthesiser comparison frequency

Main Synthesiser

FIM input frequency

Rise and fall times of inputs

FIM - FIMB Timing Skew

FIM, FIMB differential signal level

with both sides driven.

FIM single input drive level

with FIMB decoupled to VSS

FIM, FIMB common mode range

FIM, FIMB common mode range

FIM, FIMB input capacitance

FIM, FIMB differential input resistance

Delay FIM rising to MODMP/MODMN changing

Main Synthesiser comparison frequency

Min.

235

Typ.

Max.

500

-10.5

-13.5

-15

-20

Unit Conditions

mVrms Circuit as in fig. 15,

dBc

dBc

dBc

dBc

5

400

10

10

180

100

360

200

VDD – 1·7

2.8

10

4

100

200

VDD – 1·7

2·8

10

30

MHz

mVpk-pk With crystal oscillator

powered down

10

pF

kΩ

135

10

±2

or ± 10%

VDD – 0·7

VDD – 0·85

10

2

MHz May be a sinewave

ns

ns See Fig. 6

signal Both maxima

period must be met

mVpk-pk Each input, 5 to 50 &

99 to 135 MHz

mV pk-pk Each input,

50 to 99 MHz

mVpk-pk One input, 5 to 50 &

99 to 135 MHz

mVpk-pk One input,

50 to 99 MHz

V VDD = 3.6V

V VDD = 5V

pF

kΩ Note 8

MHz

20

50

±2

or ± 10%

1000

VDD – 0·7

VDD – 0·85

10

30

2

MHz

ns

ns See Fig. 6

signal Both maxima

period must be met

mVpk-pk Each input,

4 to 20 MHz

mVpk-pk One input,

4 to 20 MHz

V VDD =3.6V

V VDD =5V

pF

kΩ Note 8

ns

MHz

Note

8. To simplify single ended drive there is a resistor between FIA and FIAB and another between FIM and FIMB. In this mode the inputs should

drive FIA or FIM with D.C. coupling and the other inputs FIAB and FIMB should be decoupled to ground by external capacitors.

9

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