ACPL-072L データシートの表示（PDF） - Avago Technologies
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ACPL-072L Datasheet PDF : 11 Pages
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Application Information
Bypassing and PC Board Layout
The ACPL-x72L optocouplers are extremely easy to use.
No external interface circuitry is required because ACPL-
x72L uses high speed CMOS IC technology allowing
CMOS logic to be connected directly to the inputs and
outputs.
As shown in Figure 7, the only external components
required for proper operation are two bypass capacitors.
Capacitor values should be between 0.01mF and 0.1mF.
For each capacitor, the total lead length between both
ends of the capacitor and power supply pins should not
exceed 20mm. Figure 8 illustrates the recommended
printed circuit board layout for ACPL-x72L.
V DD1
1
C1
VI
2
NC 3
GND1
4
8
V DD2
C2
7 NC
6
VO
5
GND 2
C1, C2 = 0.01 µF TO 0.1 µF
Figure 7. Recommended Circuit Diagram
Propagation Delay, Pulse-Width Distortion and Propa-
gation Delay Skew
Propagation Delay is a figure of merit which describes
how quickly a logic signal propagates through a system.
The propagation delay from a low to high (tPLH) is the
amount of time required for an input signal to propagate
to the output, causing the output to change from low to
high. Similarly, the propagation delay from high to low
(tPHL) is the amount of time required for the input signal
to propagate to the output, causing the output to change
from high to low. Please see Figure 9.
INPUT
VI
OUTPUT
VO
t PLH
90%
10%
50%
t PHL
90%
10%
5 V CMOS
0V
V OH
2.5 V CMOS
V OL
Figure 9. Signal plot shows how propagation delay is defined
Pulse-width distortion (PWD) is the difference between
tPHL and tPLH and often determines the maximum data
rate capability of a transmission system. PWD can be
expressed in percent by dividing the PWD (in ns) by the
minimum pulse width (in ns) being transmitted. Typically,
PWD on the order of 20-30% of the minimum pulse
width is tolerable. The PWD specification for ACPL-x72L
is 6ns (15%) maximum across recommended operating
conditions.
V DD1
VI
C1
GND 1
Figure 8. Recommended Printed Circuit Board Layout
VDD2
C2
VO
GND 2
C1, C2 = 0.01 µF TO 0.1 µF
10
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