5962F9863201VCC データシートの表示（PDF） - Intersil

部品番号

コンポーネント説明

メーカー

5962F9863201VCC

Radiation Hardened Dual J-K Flip-Flop with Set and Reset

Intersil 

Data Sheet

ACS109MS

July 1999

File Number 4760

Radiation Hardened Dual J-K Flip-Flop

with Set and Reset

The Radiation Hardened ACS109MS is a Dual J-K Flip-

Flop with Set and Reset. These Flip-Flops have

independent J, K, Set, Reset, and Clock inputs and Q and

Q outputs. The outputs change state on the positive-going

transition of the clock. Set and Reset are accomplished

asynchronously by Low-level inputs. All inputs are buffered

and the outputs are designed for balanced propagation

delay and transition times.

The ACS109MS is fabricated on a CMOS Silicon on

Sapphire (SOS) process, which provides an immunity to

Single Event Latch-up and the capability of highly reliable

performance in any radiation environment. These devices

offer significant power reduction and faster performance

when compared to ALSTTL types.

Specifications for Rad Hard QML devices are controlled

by the Defense Supply Center in Columbus (DSCC). The

SMD numbers listed below must be used when ordering.

Detailed Electrical Specifications for the ACS109MS are

contained in SMD 5962-98632. A “hot-link” is provided

on our homepage for downloading.

http://www.intersil.com/spacedefense/spaceselect.htm

Ordering Information

ORDERING NUMBER

5962F9863201VCC

ACS109D/SAMPLE-03

5962F9863201VXC

ACS109K/SAMPLE-03

5962F9863201V9A

INTERNAL MARKETING

NUMBER

ACS109DMSR-03

ACS109D/SAMPLE-03

ACS109KMSR-03

ACS109K/SAMPLE-03

ACS109HMSR-03

Pinouts

ACS109MS

(SBDIP)

TOP VIEW

1R 1

1J 2

1K 3

1CP 4

1S 5

1Q 6

1Q 7

GND 8

16 VCC

15 2R

14 2J

13 2K

12 2CP

11 2S

10 2Q

9 2Q

Features

• QML Qualified Per MIL-PRF-38535 Requirements

• 1.25 Micron Radiation Hardened SOS CMOS

• Radiation Environment

- Latch-Up Free Under Any Conditions

- Total Dose (Max.) . . . . . . . . . . . . . . . . . 3 x 105 RAD(Si)

- SEU Immunity . . . . . . . . . . . . . <1 x 10-10 Errors/Bit/Day

- SEU LET Threshold . . . . . . . . . . . . >100MeV/(mg/cm2)

• Input Logic Levels. . . . VIL = (0.3)(VCC), VIH = (0.7)(VCC)

• Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . ±12mA (Min)

• Quiescent Supply Current . . . . . . . . . . . . . . . 10µA (Max)

• Propagation Delay . . . . . . . . . . . . . . . . . . . . . . 25ns (Max)

Applications

• High Speed Control Circuits

• Sensor Monitoring

• Low Power Designs

TEMP. RANGE (oC)

-55 to 125

25

-55 to 125

25

25

PACKAGE

16 Ld SBDIP

16 Ld SBDIP

16 Ld Flatpack

16 Ld Flatpack

Die

DESIGNATOR

CDIP2-T16

CDIP2-T16

CDFP4-F16

CDFP4-F16

NA

ACS109MS

(FLATPACK)

TOP VIEW

1R

1

16

VCC

1J

2

15

2R

1K

3

14

2J

1CP

4

13

2K

1S

5

12

2CP

1Q

6

11

2S

1Q

7

10

2Q

GND

8

9

2Q

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

Share Link: