VG26S18165C データシートの表示（PDF） - Vanguard International Semiconductor
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VG26S18165C Datasheet PDF : 26 Pages
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VG26(V)(S)18165C/VG26(V)(S)18165D
1,048,576 x 16 - Bit
CMOS Dynamic RAM
AC Characteristics(Ta = 0 to + 70°C, Vcc = 5V ±10 % or 3.3V ±10 %, Vss = 0V) *1, *2, *3, *4, *5
Test conditions
• Output load:
two TTL Loads and 50pF (VCC = 5.0V ±10 %); one TTL Load and 50pF (VCC = 3.3V ±10 %)
• Input timing reference levels:
VIH = 2.4V, VIL = 0.8V (VCC = 5.0V ±10 %); VIH = 2.0V, VIL = 0.8V (VCC = 3.3V ±10 %)
• Output timing reference levels:
VOH = 2.0V, VOL = 0.8V (VCC = 5V ±10 %, 3.3V ±10 %)
Read, Write, Read- Modify- Write and Refresh Cycles
(Common Parameters)
Parameter
Symbol
Random read or write cycle time
RAS precharge time
LCAS / UCAS precharge time in normal
mode
RAS pulse width
LCAS / UCAS pulse width
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to LCAS / UCAS delay time
RAS to column address delay time
Column address to RAS lead time
RAS hold time
LCAS / UCAS hold time
LCAS / UCAS to RAS precharge time
OE to Din delay time
Transition time (rise and fall)
Refresh period
LCAS / UCAS to output in Low- Z
LCAS / UCAS delay time from Din
OE delay time from Din
tRC
tRP
tCPN
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
tRAD
tRAL
tRSH
tCSH
tCRP
tOED
tT
tREF
tCLZ
tDZC
tDZO
VG26(V)(S) 18165
-5
Min
Max
84
-
-6
Unit
Min
Max
104
- ns
30
-
40
- ns
10
-
10
- ns
Notes
50 10K
8 10K
0
-
8
-
0
-
8
-
12
37
10
25
25
-
8
-
38
-
5
-
20
-
1
50
-
16
0
-
0
-
0
-
60 10K ns
6
10 10K ns
7
0
- ns
10
- ns
0
- ns
8
10
- ns
14
45 ns
9
12
30 ns
10
30
- ns
10
- ns
40
- ns
5
- ns
11
20
- ns
1
50 ns
12
-
16 ms
0
- ns
0
- ns
0
- ns
Document:1G5-0179
Rev.1
Page 8
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