ACT5230 データシートの表示（PDF） - Aeroflex Corporation
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ACT5230 Datasheet PDF : 7 Pages
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ACT5230
32-Bit Superscaler Microprocessor
Features
s Full militarized QED RM5230 microprocessor
s Dual Issue superscalar microprocessor - can issue one
integer and one floating-point instruction per cycle
q 100, 133 and 150 MHz operating frequency – Consult
Factory for latest speeds
q 228 Dhrystone2.1 MIPS
q SPECInt95 4.2 SPECfp95 4.5
s System interface optomized for embedded
applications
q 32-bit system interface lowers total system cost with up to
87.5 MHz operating frequency
q High performance write protocols maximize uncached
write bandwidth
q Operates at processor clock divisors 2 through 8
q 5V tolerant I/O's
q IEEE 1149.1 JTAG boundary scan
s Integrated on-chip caches
q 16KB instruction - 2 way set associative
q 16KB data - 2 way set associative
q Virtually indexed, physically tagged
q Write-back and write-through on per page basis
q Early restart on data cache misses
s Integrated memory management unit
q Fully associative joint TLB (shared by I and D translations)
q 48 dual entries map 96 pages
q Variable page size (4KB to 16MB in 4x increments)
s High-performance floating point unit
q Single cycle repeat rate for common single precision
operations and some double precision operations
q Two cycle repeat rate for double precision multiply and
double precision combined multiply-add operations
q Single cycle repeat rate for single precision combined
multiply-add operation
s MIPS IV instruction set
q Floating point multiply-add instruction increases
performance in signal processing and graphics
applications
q Conditional moves to reduce branch frequency
q Index address modes (register + register)
s Embedded application enhancements
q Specialized DSP integer Multiply-Accumulate instruction
and 3 operand multiply instruction
q I and D cache locking by set
q Optional dedicated exception vector for interrupts
s Fully static CMOS design with power down logic
q Standby reduced power mode with WAIT instruction
q 2.5 Watts typical with less than 70 mA standby current
s 128-pin Power Quad-4 package (F22), Consult Factory for
package configuration
Block Diagram
Data Set A
Store Buffer
Phase Lock Loop
Data Tag A
DTLB Physical
Data Tag B
Instruction Set A
Sys AD
Instruction Select
Write Buffer
Read Buffer
Data Set B
Address Buffer
Instruction Tag A
ITLB Physical
Instruction Tag B
Integer Instruction Register
FP Instruction Register
Instruction Set B
Control
DBus
Floating-point
Register File
FPIBus
Tag Aux Tag
Joint TLB
Unpacker/Packer
Floating-point
MAdd, Add, Sub,Cvt
Div, SqRt
Coprocessor 0
System/Memory
Control
DVA
IVA
PC Incrementer
Branch Adder
Instruction TLB Virtual
Program Counter
IntIBus
Load Aligner
Integer Register File
Integer/Address Adder
Data TLB Virtual
Shifter/Store Aligner
Logic Unit
ABus
Integer Multiply, Divide
Preliminary
eroflex Circuit Technology – RISC TurboEngines For The Future © SCD5230 REV 1 12/22/98
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