ACT-7000SC-150F17C データシートの表示（PDF） - Aeroflex Corporation
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ACT-7000SC-150F17C Datasheet PDF : 25 Pages
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DESCRIPTION
The ACT 7000SC is a highly integrated symmetric
superscalar microprocessor capable of issuing two
instructions each processor cycle. It has two high
performance 64-bit integer units as well as a high
throughput, fully pipelined 64-bit floating point unit. To
keep its multiple execution units running efficiently,
the ACT 7000SC integrates not only 16KB 4-way set
associative instruction and data caches but backs
them up with an integrated 256KB 4-way set
associative secondary as well. For maximum
efficiency, the data and secondary caches are
writeback and nonblocking. A RM52XX family
compatible, operating system friendly memory
management unit with a 64/48-entry fully associative
TLB and a high-performance 64-bit system interface
supporting hardware prioritized and vectored
interrupts round out the main features of the
processor.
The ACT 7000SC is ideally suited for highend
embedded control applications such as
internetworking, high performance image
manipulation, high speed printing, and 3-D
visualization.
HARDWARE OVERVIEW
The ACT 7000SC offers a high-level of integration
targeted at high-performance embedded
applications. The key elements of the ACT 7000SC
are briefly described below.
CPU Registers
Like all MIPS ISA processors, the ACT 7000SC
CPU has a simple, clean user visible state consisting
of 32 general purpose registers, or GPR’s, two special
purpose registers for integer multiplication and
division, and a program counter; there are no
condition code bits. Figure 1 shows the user visible
state.
Superscalar Dispatch
The ACT 7000SC has an efficient symmetric
superscalar dispatch unit which allows it to issue up to
two instructions per cycle. For purposes of instruction
issue, the ACT 7000SC defines four classes of
instructions: integer, load/store, branches, and
floating-point. There are two logical pipelines, the
function, or F, pipeline and the memory, or M,
pipeline. Note however that the M pipe can execute
integer as well as memory type instructions.
Table 1 – Instruction Issue Rules
F Pipe
M Pipe
one of:
integer, branch, floating-point,
integer mul, div
one of:
integer, load/store
Figure 2 is a simplification of the pipeline section
and illustrates the basics of the instruction issue
mechanism.
General Purpose Registers
63
0
0
r1
r2
•
•
•
•
r29
r30
r31
Multiply/Divide Registers
63
0
HI
63
0
LO
Program Counter
63
0
PC
Aeroflex Circuit Technology
Figure 1 – CP0 Registers
2
SCD7000SC REV B 7/30/01 Plainview NY (516) 694-6700
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