AD10226 データシートの表示（PDF） - Analog Devices
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AD10226 Datasheet PDF : 20 Pages
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AD10226
PIN CONFIGURATION
25 23 21 19 17 15 13 11 9 7 5 3
1
24 22 20 18 16 14 12 10 8 6 4
2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
Mnemonic
AGNDA
REF_A_OUT
NC
AIN A1
AIN A2
AVCCA
DGNDA
D11A–D0A
ENCODEA
ENCODEA
DVCCA
DGNDB
D11B–D0B
AGNDB
DVCCB
ENCODEB
ENCODEB
REF_B_OUT
AIN B1
AIN B2
AVCCB
DFS
SFDR Mode
REV. 0
35mm SQUARE
BOTTOM VIEW
PIN FUNCTION DESCRIPTIONS
Function
A Channel Analog Ground. A and B grounds should be connected as close to the device as possible.
A Channel Internal Voltage Reference
No connection
Analog Input for A side ADC (– input)
Analog Input for A side ADC (+ input)
Analog Positive Supply Voltage (nominally 5.0 V)
A Channel Digital Ground
Digital Outputs for ADC A. D0 (LSB)
Complement of ENCODE
Data conversion initiated on the rising edge of ENCODE input.
Digital Positive Supply Voltage (nominally 3.3 V)
B Channel Digital Ground
Digital Outputs for ADC B. D0 (LSB)
B Channel Analog Ground. A and B grounds should be connected as close to the device as possible.
Digital Positive Supply Voltage (nominally 3.3 V)
Complement of ENCODE
Data conversion initiated on rising edge of ENCODE input.
B Channel Internal Voltage Reference
Analog Input for B side ADC (– input)
Analog Input for B side ADC (+ input)
Analog Positive Supply Voltage (nominally 5.0 V)
Data format select. Low = Two’s Complement, High = Binary.
CMOS control pin that enables (SFDR MODE = 1) a proprietary circuit that may improve the spurious free dynamic
range (SFDR) performance. It is useful in applications where the dynamic range of the system is limited by discrete spurious
frequency content caused by nonlinearities in the ADC transfer function. SFDR Mode = 0 for normal operation.
–5–
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