AD10465 データシートの表示（PDF） - Analog Devices
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AD10465
Analog Devices
AD10465 Datasheet PDF : 20 Pages
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AD10465
Parameter
Test Mil
AD10465AZ/BZ/QML-H
Temp Level Subgroup Min Typ
Max Unit
SPURIOUS-FREE DYNAMIC RANGE8
Analog Input @ 4.98 MHz
Analog Input @ 9.9 MHz
Analog Input @ 19.5 MHz
Analog Input @ 32.1 MHz
25°C V
25°C I
4
Full
II
5, 6
25°C I
4
Full
II
5, 6
25°C I
4
Full
II
5, 6
85
73
82
70
82
72
78
70
78
62
68
60
66
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
TWO-TONE IMD REJECTION9
fIN = 10 MHz and 11 MHz
f1 and f2 are –7 dB
fIN = 31 MHz and 32 MHz
f1 and f2 Are –7 dB
CHANNEL-TO-CHANNEL ISOLATION10
25°C I
4
II
5, 6
25°C I
4
Full
II
5, 6
25°C IV
12
78
87
78
68
70
60
90
dBFS
dBFS
dB
TRANSIENT RESPONSE
25°C V
15.3
ns
OVERVOLTAGE RECOVERY TIME11
VIN = 2.0 × fS
VIN = 4.0 × fS
DIGITAL OUTPUTS12
Logic Compatibility
DVCC = 3.3 V
Logic “1” Voltage
Logic “0” Voltage
DVCC = 5 V
Logic “1” Voltage
Logic “0” Voltage
Output Coding
Full
IV
Full
IV
Full
I
Full
I
Full
V
Full
V
12
12
1, 2, 3
1, 2, 3
40
100 ns
150
200 ns
CMOS
2.5
DVCC – 0.2
V
0.2
0.5
V
DVCC – 0.3
V
0.35
V
Two’s Complement
POWER SUPPLY
AVCC Supply Voltage13
I (AVCC) Current
AVEE Supply Voltage13
I (AVEE) Current
DVCC Supply Voltage13
I (DVCC) Current
ICC (Total) Supply Current per Channel
Power Dissipation (Total)
Power Supply Rejection Ratio (PSRR)
Passband Ripple to 10 MHz
Passband Ripple to 25 MHz
Full
VI
Full
I
Full
VI
Full
V
Full
VI
Full
V
Full
I
Full
I
Full
V
V
V
1, 2, 3
1, 2, 3
4.85 5.0
270
–5.25 –5.0
38
3.135 3.3
30
338
3.5
0.02
0.1
0.2
5.25
308
–4.75
49
3.465
46
403
3.9
V
mA
V
mA
V
mA
mA
W
% FSR/% VS
dB
dB
NOTES
1 Gain tests are performed on AIN1 input voltage range.
2 Input Capacitance spec. combines AD8037 die capacitance and ceramic package capacitance.
3 Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB.
4 All ac specifications tested by driving ENCODE and ENCODE differentially.
5 Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50% ± 5%.
6 Analog input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed). Encode = 65 MSPS. SNR
is reported in dBFS, related back to converter full power.
7 Analog input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 65 MSPS.
8 Analog input signal power swept from –1 dBFS to –60 dBFS; SFDR is ratio of converter full scale to worst spur.
9 Both input tones at –7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product.
10Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B channel.
11 Input driven to 2× and 4× AIN1 range for > four clock cycles. Output recovers inband in specified time with Encode = 65 MSPS.
12 Digital output logic levels: DVCC = 3.3 V, CLOAD = 10 pF. Capacitive loads > 10 pF will degrade performance.
13 Supply voltage recommended operating range. AVCC may be varied from 4.85 V to 5.25 V. However, rated ac (harmonics) performance is valid only over the range
AVCC = 5.0 V to 5.25 V.
All specifications guaranteed within 100 ms of initial power-up regardless of sequencing.
Specifications subject to change without notice.
REV. 0
–3–
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