AD1812 データシートの表示（PDF） - Analog Devices
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AD1812 Datasheet PDF : 20 Pages
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AD1812
TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE)
Parameter
Symbol
Min
Typ
Max
Units
IOW/IOR Strobe Width
IOW/IOR Rising to IOW/IOR Falling
Write Data Setup to IOW Rising
IOR Falling to Valid Read Data
AEN Setup to IOW/IOR Falling
AEN Hold from IOW/IOR Rising
Adr Setup to IOW/IOR Falling
Adr Hold from IOW/IOR Rising
DACK Rising to IOW/IOR Falling
IOW/IOR Rising to DACK Falling
DACK Setup to IOW/IOR Falling
Data Hold from IOR Rising
Data Hold from IOW Rising
DRQ Hold from IOW/IOR Falling
DACK Hold from IOW Rising
DACK Hold from IOR Rising
tSTW
100
tBWDN
80
tWDSU
10
tRDDV
tAESU
10
tAEHD
0
tADSU
10
tADHD
10
tDKSU1
20
tDKHD1
0
tDKSU2
10
tDHD1
tDHD2
15
tDRHD
tDKHD2
10
tDKHD3
10
ns
ns
ns
40
ns
ns
ns
ns
ns
ns
ns
ns
20
ns
ns
25
ns
ns
ns
*Guaranteed, not tested.
Specifications subject to change without notice.
General Notes
Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield
meaningful results for an additional device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, you cannot meaningfully add
up parameters to derive longer times. Note that all 8-bit DMA transfers occur on channels 0, 1, and 3, while all 16-bit DMA transfers occur on channels 5, 6, and 7.
DRQ
(0, 1, 3, 5, 6, 7)
DACK
(0, 1, 3, 5, 6, 7)
AEN
IOR
PC_D (7:0) /
PC_D (15:0)
PC_A (15:0)
tDKSU1
tAESU
tDKHD1
tAEHD
tSTW
tADSU
tRDDV
tDHD1
tADHD
Figure 1. PIO Read Cycle
DRQ
(0, 1, 3, 5, 6, 7)
DACK
(0, 1, 3, 5, 6, 7)
AEN
IOR
PC_D (7:0) /
PC_D (15:0)
tDKSU2
tAESU
tDRHD
tSTW
tRDDV
tDKHD3
tAEHD
tDHD1
DRQ
(0, 1, 3, 5, 6, 7)
DACK
(0, 1, 3, 5, 6, 7)
AEN
IOW
PC_D (7:0) /
PC_D (15:0)
PC_A (15:0)
DRQ
(0, 1, 3, 5, 6, 7)
DACK
(0, 1, 3, 5, 6, 7)
AEN
IOW
PC_D (7:0) /
PC_D (15:0)
tDKSU1
tAESU
tADSU
tSTW
tWDSU
tDKHD1
tAEHD
tDHD2
tADHD
Figure 2. PIO Write Cycle
tDKSU2
tAESU
tDRHD
tSTW
tWDSU
tDKHD2
tAEHD
tDHD2
Figure 3. DMA Read Cycle
Figure 4. DMA Write Cycle
REV. 0
–5–
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