AD12401-400JWS データシートの表示（PDF） - Analog Devices
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AD12401-400JWS Datasheet PDF : 28 Pages
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Table 7. Output Coding (Twos Complement)
AIN (V)
Code KWS
JWS
Digital Output
4095 +1.6
+0.8
0111 1111 1111
.
.
.
.
.
.
.
.
.
.
.
.
2048 0
0
0000 0000 0000
2047 −0.000781 to +0.0003905
1111 1111 1111
.
.
.
.
.
.
.
.
0
−1.6 to
+0.8
1000 0000 0000
AD12401
Table 8. Option Pin List with Necessary Associated Circuitry
Pin
Name
Logic
Active Level
High Type
Default Associated Circuitry
Level Within Part
RESET Low LVTTL High
3.74 kΩ Pull-Up
DR_EN High LVTTL High
Weak Pull-Up (>16 kΩ)
ENCODE
ENCODE
3.3V
100Ω
3.3V
100Ω
100Ω PECL
DRIVER
100Ω
Figure 2. ENCODE Equivalent Circuit
N–1 N N+1
N+2
N+3
tEL
tEH
ENC
400MHZ
DATA OUT A
1/fS
74 CLOCK CYCLES
N – 74 N – 73
1
N
N+2
N+4
N+6
N+8
DRA
DRA
DATA OUT B
N+1
N+3
1
N+5
N+7
DRB
DRB
DR_EN
NOTES
1. DATA LOST DUE TO ASSERTION OF DR_EN. LATENCY OF 74 ENCODE CLOCK CYCLES BEFORE DATA VALID.
2. IF A SINGLE-ENDED SINE WAVE IS USED FOR ENCODE, USE THE ZERO CROSSING POINT (AC-COUPLED) AS
THE 50% POINT AND APPLY THE SAME TIMING INFORMATION.
3. THE DR_EN PIN IS USED TO SYNCHRONIZE THE COLLECTION OF DATA INTO EXTERNAL BUFFER MEMORIES.
THE DR_EN PIN CAN BE APPLIED SYNCHRONOUSLY OR ASYNCHRONOUSLY TO THE AD12401. IF APPLIED
ASYNCHRONOUSLY, DR_EN MUST BE HELD LOW FOR A MINIMUM OF 5ns TO ENSURE CORRECT OPERATION.
THE FUNCTION SHUTS OFF DRA AND DRB UNTIL THE DR_EN PIN IS SET HIGH AGAIN. DRA AND DRB RESUME
ON THE NEXT VALID DRA AFTER DR_EN IS RETURNED HIGH. IF THIS FEATURE IS NOT REQUIRED, TIE THIS
PIN TO 3.3V THROUGH A 3.74kΩ RESISTOR OR LEAVE IT FLOATING.
Figure 3. Timing Diagram
ENC
ENC
DATA OUT
tEDR
tPD
tVD
DR
DR
Figure 4. Highlighted Timing Diagram
Rev. A | Page 9 of 28
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