AD1958YRS データシートの表示（PDF） - Analog Devices
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AD1958YRS Datasheet PDF : 8 Pages
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AD1958
TEMPERATURE RANGE
Min
Typ
Max
Specifications Guaranteed
Functionality Guaranteed
Storage
25
–40
–55
+105*
+125
NOTE
*105°C ambient guaranteed for a 4-layer board, two 1 oz. planes, two 2 oz. signal layers. Derate to 85 °C for 2-layer board, 2 oz. layers.
Specifications subject to change without notice.
Unit
°C
°C
°C
POWER
Min
Typ
Max
Unit
Supplies
Voltage, Analog Digital PLL
4.50
5
5.50
V
Analog Current
36
41
mA
Digital Current
25
29
mA
PLL Current
30
34
mA
Dissipation
E Operation—All Supplies
455
540
mW
Operation—Analog Supply
180
mW
Operation—Digital Supply
125
mW
T Operation—PLL Supply
150
mW
Power Supply Rejection Ratio
1 kHz 300 mV p-p Signal at Analog Supply Pins
–60
dB
20 kHz 300 mV p-p Signal at Analog Supply Pins
–50
dB
E Specifications subject to change without notice.
DIGITAL FILTER CHARACTERISTICS
L Sample Rate (kHz) Pass Band (kHz)
44.1
DC–20
48
DC–21.8
96
DC–39.95
O 192
DC–87.2
Specifications subject to change without notice.
Stop Band (kHz)
24.1–328.7
26.23–358.28
56.9–327.65
117–327.65
Stop Band Attenuation (dB)
75
75
75
60
Pass Band Ripple (dB)
± 0.0002
± 0.0002
± 0.0005
0/–0.04 (DC–21.8 kHz)
0/–0.5 (DC–65.4 kHz)
0/–1.5 (DC–87.2 kHz)
S GROUP DELAY
Chip Mode
Group Delay Calculation
B INT8× Mode
INT4× Mode
INT2× Mode
24.625/fS
15.75/fS
14/fS
O Specifications subject to change without notice.
fS
48 kHz
96 kHz
192 kHz
Group Delay
513
164
72.91
Unit
µs
µs
µs
DIGITAL TIMING (Guaranteed over –40°C to +105؇C, AVDD = DVDD = PVDD = 5.0 V ؎ 10%)
Min
Unit
tDMP
MCLK Period (FMCLK = 256 × FLRCLK)
54
ns
tDML
MCLK LO Pulsewidth (All Modes)
15
ns
tDMH
MCLK HI Pulsewidth (All Modes)
10
ns
tDBH
BCLK HI Pulsewidth
20
ns
tDBL
BCLK LO Pulsewidth
20
ns
tDBP
BCLK Period
60
ns
tDLS
LRCLK Setup
20
ns
tDLH
LRCLK Hold (DSP Serial Port Mode Only)
20
ns
tDDS
SDATA Setup
15
ns
tDDH
SDATA Hold
15
ns
tRSTL
RST LO Pulsewidth
15
ns
Specifications subject to change without notice.
REV. 0
–3–
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