AD1958YRS データシートの表示（PDF） - Analog Devices

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AD1958YRS

PLL/Multibit Σ-Δ DAC

Analog Devices 

AD1958

PIN FUNCTION DESCRIPTIONS

Pin

Input/Output Mnemonic

Description

1

I

CCLK

Control Clock Input for Control Data. Control input data must be valid on

the rising edge of CCLK. CCLK may be continuous or gated.

2

I

CLATCH

Latch Input for Control Data

3

I

RESET

Reset. The AD1958 is placed in a reset mode when this pin is held LO.

The serial control port registers are reset to their default values. Set HI for

normal operation.

4

I

LRCLK

Left/Right Clock Input for Input Data. Must run continuously.

5

I

BCLK

Bit Clock Input for Input Data. Need not run continuously; may be gated

or used in a burst fashion.

6

I

7

I

8

I

9

O

E 10

O

11

O

12

I/O

T 13

O

14

I

15

E 16

17

18

L 19

20

O

21

O

O 22

I

23

O

24

25

S 26

O

27

I

B 28

I

SDATA

DVDD

DGND

SCLK0

SCLK1

SCLK2

MCLK

XOUT

XIN

PVDD

PGND

LF0

LF1

AGND0

OUTR

FILTR

AGND1

OUTL

AVDD

FILTB

ZERO

MUTE

CDATA

O FUNCTIONAL DESCRIPTION

Serial input, MSB first, containing two channels of 16/20/24 bits of two’s-

complement data per channel.

Digital Power Supply Connect to Digital 5 V Supply

Digital Ground

33.8688 MHz Clock Output

256/384/512/768 fS Output

16.9344 MHz/22.5792 MHz/512 fS Output

27 MHz Master Clock Output/256 fS DAC Clock Input

27 MHz Crystal Oscillator Output

27 MHz Crystal Oscillator/External Clock Input

PLL Power Supply. Connect to PLL 5 V Supply.

PLL Ground

PLL0 Loop Filter

PLL1 Loop Filter

Analog Ground

Right Channel Positive Line Level Analog Output

Voltage Reference Filter Capacitor Connection. Bypass and decouple the

voltage reference with parallel 10 µF and 0.1 µF capacitors to AGND.

Analog Ground

Left Channel Line Level Analog Output

Analog Power Supply. Connect to Analog 5 V Supply.

Filter Capacitor Connection. Connect 10 µF Capacitor to AGND.

Zero Flag Output. This pin goes HI when both channels have zero signal

input for more than 1024 L/R Clock Cycles.

Mute. Assert HI to Mute Both Stereo Analog Outputs. Deassert LO for

normal operation.

Serial Control Input, MSB first, containing 16 bits of unsigned data

per channel. Used for specifying channel-specific attenuation and mute.

into the audio band; care should be exercised in selecting

DAC

these components.

The AD1958 has two DAC channels arranged as a stereo pair

with single-ended analog outputs. Each channel has its own

independently programmable attenuator, adjustable in 16384

linear steps. Digital inputs are supplied through a serial data

input pin, SDATA, a frame clock, LRCLK, and a bit clock, BLCK.

The FILTB and FILTR pins should be bypassed by external

capacitors to ground. The FILTB pin is used to reduce the noise

of the internal DAC bias circuitry, thereby reducing the DAC

output noise. The voltage at the VREF pin, FILTR (VREF ~ 2.39 V)

can be used to bias external op amps used to filter the output signals.

Each analog output pin sits at a dc level of VREF (present at

FILTR), and swings ± 1.585 V for a 0 dB digital input signal.

A single op amp third-order external low-pass filter is recom-

mended to remove high-frequency noise present on the output

pins. The output phase can be changed in an SPI control

register to accommodate inverting and noninverting filters.

Note that the use of op amps with low slew rate or low band-

width may cause high frequency noise and tones to fold down

The DAC master clock frequency is 256 fS for the 32 kHz–48 kHz

range (8ϫ interpolation, see Table I). For the 96 kHz range (4ϫ

interpolation) this is 128 fS. At 192 kHz (2ϫ interpolation), this

is 64 fS. It is supplied internally from the PLL clock system when

MCLK mode is set to Output in the PLL Control Register.

When the MCLK mode is changed to Input, it must be supplied

from an external source connected to MCLK. The output from

the 27 MHz PLL clock is disabled in this case.

REV. 0

–5–

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