AD1958YRS データシートの表示（PDF） - Analog Devices
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AD1958YRS Datasheet PDF : 8 Pages
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AD1958
Bit 11:10
Interpolation
Factor
00 = 8×*
01 = 4×
10 = 2×
11 = Not Allowed
*Default Setting
Bit 9:8
Serial Data
Width
00 = 24 Bits*
01 = 20 Bits
10 = 16 Bits
11 = 16 Bits
Table I. DAC Control Register
Bit 7
Output Phase
0 = Noninverted*
1 = Inverted
Bit 6
Soft Mute
0 = No Mute*
1 = Muted
Bit 5:4
Serial Data
Format
00 = I2S*
00 = Right Justified
10 = DSP
11 = Left Justified
Bit 3:2
De-Emphasis
Filter
00 = None*
01 = 44.1 kHz
10 = 32 kHz
11 = 48 kHz
Bit 1:0
SPI Register
Address
01
PLL CLOCK SYSTEM
Table II. DAC Volume Registers
The PLL clock system is expected to be run from a 27 MHz
master clock supplied by the on-board crystal oscillator or an
external source connected to XIN. With the MCLK mode set
to Output, the 27 MHz clock is buffered out to the MCLK
pin. When set to Input, this pin is the 256 fS master clock input
E for the DAC. SCLK0 is always set to 33.8688 MHz. SCLK1 is
intended to be used as a master audio clock and will be a multiple
of the sample rate set in the PLL control register (see Table III).
In Mode 0 (Bit 8), it can be set to 512 or 768 times either
T 44.1 kHz or 48 kHz. SCLK2 will be 16.3944 MHz (384 ϫ
44.1 kHz). In Mode 1, SCLK1 can be set to 256, 384, 512,
or 768 times 32 kHz, 44.1 kHz, or 48 kHz. SCLK2 can be
set to a constant 22.5792 MHz (512 ϫ 44.1 kHz) or 512 fS.
E There are two loop filter pins, LF0 and LF1. They should each
be bypassed to PVDD by a network consisting of a 33 nF capaci-
tor in series with a 750 Ω resistor, paralleled with a 1.8 nF capacitor.
L The 27 MHz Master Clock oscillator should have a crystal cut for
an 18 pF load connected between XIN and XOUT, with 22 pF
capacitors connected from XIN and XOUT to PGND.
Bit 15:2
Volume
14 Bits, Unsigned
14 Bits, Unsigned
Default is full volume
Bit 1:0
SPI Register Address
00 = Left Volume
10 = Right Volume
RESET/POWER-DOWN
RESET will set the control registers to their default settings. The
chip should be reset on power-up. After reset is deasserted, the
part will come out of reset on the next rising LRCLK.
SERIAL CONTROL PORT
The AD1958 has an SPI-compatible control port to permit
programming the internal control registers for the PLL and DAC.
The DAC output levels may be independently programmed
by means of an internal digital attenuator adjustable in 16384
linear steps.
O Bit 11
S PLL2
Power-
Down
0 = On1
OB 1 = PD
Bit 10
PLL1
Power-
Down
0 = On1
1 = PD
Bit 9
XTAL
Power-
Down
0 = On1
1 = PD
Bit 8
Table III. PLL Control Register
Bit 7:6
Bit 5
Bit 4
Clock
Configuration
0 = Mode 01
SCLK1
fS
Select
SCLK1 =
000: 36.864 MHz1
100: 24.576 MHz
110: 33.8688 MHz
111: 22.5792 MHz
Frequency
Double2
Reserved
Set to 0
Bit 3
SCLK2
Select
Reserved
Set to 0
Bit 2
Bit 1:0
MCLK
Mode
SPI
Register
Address
0 = Output1 11
1 = Input
Other combinations reserved
SCLK2 = 16.9344 MHz
1 = Mode 1
00 = 48 kHz
01 = Not
Allowed
10 = 32 kHz
11 = 44.1 kHz
0 = 256 fS
1 = 384 fS
NOTES
1Default Setting
2In Mode 1, Frequency Double affects SCLK1 always and SCLK2 in 512 ϫ fS mode.
0 = Normal 0 = 22.5792 MHz
1=
1 = 512 ϫ fS2
fNOMINAL ϫ 2
–6–
REV. 0
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