AD5201 データシートの表示（PDF） - Analog Devices
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AD5201 Datasheet PDF : 16 Pages
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AD5200/AD5201–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (VDD = 5 V ؎ 10%, or 3 V ؎ 10%, VSS = 0 V, VA = +VDD, VB = 0 V, –40؇C < TA < +85؇C
unless otherwise noted.)
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
INTERFACE TIMING CHARACTERISTICS (Applies to All Parts [Notes 2, 3])
Input Clock Pulsewidth
tCH, tCL
Clock Level High or Low
20
ns
Data Setup Time
tDS
5
ns
Data Hold Time
CS Setup Time
CS High Pulsewidth
CLK Fall to CS Fall Hold Time
CLK Fall to CS Rise Hold Time
CS Rise to Clock Rise Setup
tDH
tCSS
tCSW
tCSH0
tCSH1
tCS1
5
ns
15
ns
40
ns
0
ns
0
ns
10
ns
NOTES
1Typicals represent average readings at 25°C and VDD = 5 V, VSS = 0 V.
2Guaranteed by design and not subject to production test.
3See timing diagram for location of measured values. All input control voltages are specified with t R = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of
1.5 V. Switching characteristics are measured using VLOGIC = 5 V.
Specifications subject to change without notice.
1
SDI
0
1
CLK
0
1
CS
0
1
VOUT
0
D7 D6 D5 D4 D3 D2 D1 D0
DAC REGISTER LOAD
Figure 1a. AD5200 Timing Diagram
1
SDI
0
1
CLK
0
1
CS
0
1
VOUT
0
D5 D4 D3 D2 D1 D0
DAC REGISTER LOAD
Figure 1b. AD5201 Timing Diagram
1
SDI
(DATA IN)
0
1
Dx
tCH
CLK
0
tCSH0
1
CS
tCSS
0
VDD
VOUT
0
Dx
tDS
tCL
tDH
tCS1
tCSH1
tCSW
tS
Figure 1c. Detail Timing Diagram
؉1LSB
–4–
REV. B
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