EVAL-AD5405EB(Rev0) データシートの表示（PDF） - Analog Devices
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EVAL-AD5405EB
(Rev.:Rev0)
(Rev.:Rev0)
Analog Devices
EVAL-AD5405EB Datasheet PDF : 24 Pages
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AD5405
SPECIFICATIONS1
VDD = 2.5 V to 5.5 V, VREFA = VREFB = 10 V, IOUT2 = 0 V. All specifications TMIN to TMAX, unless otherwise noted. DC performance measured
with OP1177, AC performance with AD9631, unless otherwise noted.
Table 1.
Parameter
STATIC PERFORMANCE
Resolution
Relative Accuracy
Differential Nonlinearity
Gain Error
Gain Error Temp Coefficient2
Bipolar Zero-Code Error
Output Leakage Current
REFERENCE INPUT2
Reference Input Range
VREFA, VREFB Input Resistance
VREFA to VREFB Input Resistance
Mismatch
R1, RFB Resistance
R2, R3 Resistance
R2 to R3 Resistance Mismatch
DIGITAL INPUTS/OUTPUT2
Input High Voltage, VIH
Input Low Voltage, VIL
Input Leakage Current, IIL
Input Capacitance
VDD = 4.5 V to 5.5 V
Output Low Voltage, VOL
Output High Voltage, VOH
VDD = 2.5 V to 3.6 V
Output Low Voltage, VOL
Output High Voltage, VOH
DYNAMIC PERFORMANCE2
Reference Multiplying BW
Output Voltage Settling Time
Digital Delay
Digital-to-Analog Glitch Impulse
Multiplying Feedthrough Error
Output Capacitance
Digital Feedthrough
Total Harmonic Distortion
Output Noise Spectral Density
Min
Typ Max Unit
Conditions
12
Bits
±1
LSB
−1/+2 LSB
Guaranteed monotonic
±25 mV
±5
ppm FSR/°C
±25 mV
±1
nA
Data = 0x0000, TA = 25°C, IOUT1
±10 nA
Data = 0x0000H, IOUT1
Typical resistor TC = −50 ppm/°C
±10
V
8
10 12
kΩ
DAC input resistance
1.6 2.5
%
Typ = 25°C, Max = 125°C
16
20 24
kΩ
16
20 24
kΩ
.06 .18
%
Typ = 25°C, Max = 125°C
1.7
V
VDD = 2.5 V to 5.5 V
0.8
V
VDD = 2.7 V to 5.5 V
0.7
V
VDD = 2.5 V to 2.7 V
1
µA
10
pF
VDD − 1
0.4
V
V
ISINK = 200 µA
ISOURCE = 200 µA
VDD −0.5
0.4
V
V
ISINK = 200 µA
ISOURCE = 200 µA
10
80 120
20 40
3
−75
2
4
5
−75
−75
25
MHz
ns
ns
nV-s
dB
pF
pF
nV-s
dB
dB
nV/√Hz
VREF = 5 V pk-pk, DAC loaded all 1s
Measured to ±1 mV of FS. RLOAD = 100 Ω, CLOAD =15 pF.
DAC latch alternately loaded with 0s and 1s.
1 LSB change around major carry, VREF = 0 V
DAC latch loaded with all 0s. Reference = 10 kHz
DAC latches loaded with all 0s
DAC latches loaded with all 1s
Feedthrough to DAC output with CS high and
alternate loading of all 0s and all 1s
VREF = 5 V p-p, all 1s loaded, f = 1 kHz
VREF = 5 V, sine wave generated from digital code
@ 1 kHz
Rev. 0 | Page 3 of 24
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