AD5415YRUZ-REEL(RevF) データシートの表示（PDF） - Analog Devices
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AD5415YRUZ-REEL
(Rev.:RevF)
(Rev.:RevF)
Analog Devices
AD5415YRUZ-REEL Datasheet PDF : 27 Pages
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Data Sheet
AD5415
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V,
VREF = 10 V, IOUT2 = 0 V, temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1
fSCLK
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t123
Update Rate
Limit at TMIN, TMAX
50
20
8
8
13
5
4
5
30
0
12
10
25
60
2.47
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
MSPS
Test Conditions/Comments2
Maximum clock frequency
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
Data setup time
Data hold time
SYNC rising edge to SCLK falling edge
Minimum SYNC high time
SCLK falling edge to LDAC falling edge
LDAC pulse width
SCLK falling edge to LDAC rising edge
SCLK active edge to SDO valid, strong SDO driver
SCLK active edge to SDO valid, weak SDO driver
Consists of cycle time, SYNC high time, data setup, and output voltage settling time
1 Guaranteed by design and characterization, not subject to production test.
2 Falling or rising edge as determined by the control bits of the serial word. Strong or weak SDO driver selected via the control register.
3 Daisy-chain and readback modes cannot operate at maximum clock frequency. SDO timing specifications measured with a load circuit, as shown in Figure 5.
t1
SCLK
SYNC
t8
t4
t2
t3
t7
t6
t5
DIN
LDAC1
DB15
DB0
t10
t9
t11
LDAC2
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
NOTES
ALTERNATIVELY, DATA CAN BE CLOCKED INTO THE INPUT SHIFT REGISTER ON THE RISING EDGE OF SCLK AS
DETERMINED BY THE CONTROL BITS. TIMING IS AS ABOVE, WITH SCLK INVERTED.
Figure 2. Standalone Mode Timing Diagram
Rev. F | Page 5 of 27
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