AD5415(Rev0) データシートの表示（PDF） - Analog Devices

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AD5415
(Rev.:Rev0)

Dual 12-Bit, High Bandwidth, Multiplying DAC with 4-Quadrant Resistors and Serial Interface

Analog Devices 

AD5415

SCLK

SYNC

SDIN

SDO

t4

DB15

(N)

t6

t5

t1

t2

t3

DB0

(N)

t12

DB15

(N+1)

DB15

(N)

ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS

DETERMINED BY CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON FALLING

EDGE OF SCLK. TIMING AS ABOVE, WITH SCLK INVERTED.

Figure 3. Daisy-Chain and Readback Modes Timing Diagram

200µA

IOL

TO OUTPUT

PIN CL

50pF

200µA

IOH

VOH (MIN) + VOL (MAX)

2

Figure 4. Load Circuit for SDO Timing Specifications

t7

t8

DB0

(N+1)

DB0

(N)

Rev. 0 | Page 6 of 28

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