AD5415YRUZ-REEL(RevF) データシートの表示（PDF） - Analog Devices

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AD5415YRUZ-REEL
(Rev.:RevF)

Dual 12-Bit, High Bandwidth, Multiplying DAC with 4-Quadrant Resistors and Serial Interface

Analog Devices 

AD5415

Data Sheet

SCLK

SYNC

SDIN

SDO

t4

DB15

(N)

t6

t5

t1

t2

t3

DB0

(N)

t12

DB15

(N + 1)

DB15

(N)

t7

t8

DB0

(N + 1)

DB0

(N)

NOTES

1. ALTERNATIVELY, DATA CAN BE CLOCKED INTO THE INPUT SHIFT REGISTER ON THE RISING EDGE OF SCLK AS

DETERMINED BY THE CONTROL BITS. IN THIS CASE, DATA IS CLOCKED OUT OF SDO ON THE FALLING

EDGE OF SCLK. TIMING IS AS ABOVE, WITH SCLK INVERTED.

Figure 3. Daisy-Chain Timing Diagram

SCLK

16

32

SYNC

SDIN

SDO

DB15

DB0

DB15

INPUT WORD SPECIFIES

REGISTER TO BE READ

DB15

NOP CONDITION

UNDEFINED

SELECTED REGISTER DATA

CLOCKED OUT

Figure 4. Readback Mode Timing Diagram

200µA

IOL

TO OUTPUT

PIN CL

50pF

VOH (MIN) + VOL (MAX)

2

200µA

IOH

Figure 5. Load Circuit for SDO Timing Specifications

DB0

DB0

Rev. F | Page 6 of 27

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