AD5541CR(1999) データシートの表示（PDF） - Analog Devices
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AD5541CR Datasheet PDF : 12 Pages
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AD5541/AD5542
TIMING CHARACTERISTICS1, 2 (VDD = 5 V ؎ 5%, VREF = 2.5 V, AGND = DGND = 0 V. All specifications TA = TMIN to TMAX, unless
otherwise noted.)
Parameter
Limit at TMIN, TMAX
All Versions
Unit
Description
fSCLK
25
t1
40
t2
20
t3
20
t4
15
t5
15
t6
35
t7
20
t8
15
t9
0
t10
30
t11
30
t12
30
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK Cycle Frequency
SCLK Cycle Time
SCLK High Time
SCLK Low Time
CS Low to SCLK High Setup
CS High to SCLK High Setup
SCLK High to CS Low Hold Time
SCLK High to CS High Hold Time
Data Setup Time
Data Hold Time
LDAC Pulsewidth
CS High to LDAC Low Setup
CS High Time Between Active Periods
NOTES
1Guaranteed by design. Not production tested.
2Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5␣ ns (10% to
90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
Specifications subject to change without notice.
SCLK
CS
DIN
LDAC*
t6
t4
t 12
t8
t9
DB15
t1
t2
t3
t5
t7
DB0
t 11
t 10
*AD5542 ONLY. MAY BE TIED PERMANENTLY LOW IF REQUIRED.
Figure 1. Timing Diagram
REV. A
–3–
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