AD5543 データシートの表示（PDF） - Analog Devices
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AD5543 Datasheet PDF : 20 Pages
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Data Sheet
APPLICATIONS INFORMATION
STABILITY
VDD
U1
VDD
RFB
C1
VREF
VREF
GND
IOUT
VO
AD8628
AD5543/AD5553
U2
Figure 21. Optional Compensation Capacitor for Gain Peaking Prevention
In the I-to-V configuration, the IOUT of the DAC and the inverting
node of the operational amplifier must be connected as close as
possible to each other, and proper PCB layout technique must be
employed. Because every code change corresponds to a step
function, gain peaking may occur if the operational amplifier has
limited gain bandwidth product (GBP) and there is excessive
parasitic capacitance at the inverting node.
An optional compensation capacitor, C1, can be added for
stability, as shown in Figure 21. C1 must be found empirically,
but 20 pF is generally adequate for the compensation.
AD5543/AD5553
BIPOLAR OUTPUT
The AD5543/AD5553 are inherently 2-quadrant multiplying
DACs. That is, they can easily be set up for unipolar output
operation. The full-scale output polarity is the inverse of the
reference input voltage.
In some applications, it may be necessary to generate the full
4-quadrant multiplying capability or a bipolar output swing, which
is easily accomplished by using an additional U4 external amplifier
configured as a summing amplifier (see Figure 22). In this circuit,
the second amplifier, U4, provides a gain of 2 that increases the
output span magnitude to 5 V. Biasing the external amplifier with a
2.5 V offset from the reference voltage results in a full 4-quadrant
multiplying circuit. The transfer equation of this circuit shows
that both negative and positive output voltages are created as the
input data (D) is incremented from code zero (VOUT = −2.5 V)
to midscale (VOUT = 0 V) to full-scale (VOUT = +2.5 V).
VOUT = (D/32,768 − 1) × VREF (AD5543)
(3)
VOUT = (D/16,384 − 1) × VREF (AD5553)
(4)
For the AD5543, the resistance tolerance becomes the dominant
error of which users must be aware.
R1 R2
10kΩ ± 0.01% 10kΩ ± 0.01%
C2
+5V
ADR03 U1
VDD RFB
C1
U4 +5V
5kΩ ± 0.01%
R3
V+
VO
1/2AD8620
V–
+5V VOUT VIN
GND
U3
VREF
GND
IOUT
1/2AD8620
–5V
–2.5V < VO < +2.5V
AD5553 ONLY
U2
Figure 22. 4-Quadrant Multiplying Application Circuit
Rev. G | Page 11 of 20
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