AD5543 データシートの表示（PDF） - Analog Devices
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AD5543 Datasheet PDF : 20 Pages
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AD5543/AD5553
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CLK 1
SDI 2
RFB 3
VREF 4
AD5543/
AD5553
TOP VIEW
(Not to Scale)
8 CS
7 VDD
6 GND
5 IOUT
Figure 6. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1
CLK
Clock Input. Positive edge triggered, clocks data into shift register.
2
SDI
Serial Register Input. Data loads directly into the shift register MSB first. Extra leading bits are ignored.
3
RFB
Internal Matching Feedback Resistor. This pin connects to an external operational amplifier for voltage output.
4
VREF
DAC Reference Input Pin. Establishes DAC full-scale voltage. Constant input resistance vs. code.
5
IOUT
DAC Current Output. This pin connects to the inverting terminal of the external precision I-to-V operational
amplifier for voltage output.
6
GND
Analog and Digital Ground.
7
VDD
Positive Power Supply Input. Specified range of operation at 5 V ± 10%.
8
CS
Chip Select. Active low digital input. Transfers shift register data to DAC register on rising edge.
See Table 4 for operation.
Table 4. Control Logic Truth Table
CLK
CS
Serial Shift Register Function
X
H
No effect
↑+1
L
Shift register data advanced one bit
X1
H
No effect
X1
↑+1 Shift register data transferred to DAC register
1 ↑+ = positive logic transition; X means don't care.
DAC Register
Latched
Latched
Latched
New data loaded from serial register
Rev. G | Page 6 of 20
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