EVAL-AD5760SDZ データシートの表示（PDF） - Analog Devices

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EVAL-AD5760SDZ

Ultra Stable, 16-Bit ±0.5 LSB INL, Voltage Output DAC

Analog Devices 

AD5760

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Companion Products ....................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ............................................. 9

Terminology .................................................................................... 17

Theory of Operation ...................................................................... 18

REVISION HISTORY

4/2018—Rev. E to Rev. F

Added Power-Up Sequence Section and Figure 50; Renumbered

Sequentially ..................................................................................... 23

Updated Outline Dimensions ....................................................... 27

Changes to Ordering Guide .......................................................... 27

10/2016—Rev. D to Rev. E

Changes to Figure 4 and Table 5..................................................... 8

Changes to Figure 42, Figure 43, and Figure 44 ......................... 15

7/2013—Rev. C to Rev. D

Changes to t1 Test Conditions/Comments and Endnote 2 ......... 5

Deleted Figure 4 ................................................................................ 7

Changes to Pin 11 Description ....................................................... 8

Deleted Daisy-Chain Operation Section..................................... 20

Data Sheet

DAC Architecture....................................................................... 18

Serial Interface ............................................................................ 18

Hardware Control Pins.............................................................. 19

On-Chip Registers...................................................................... 19

AD5760 Features ............................................................................ 23

Power-On to 0 V......................................................................... 23

Power-Up Sequence ................................................................... 23

Configuring the AD5760 .......................................................... 23

DAC Output State ...................................................................... 23

Output Amplifier Configuration.............................................. 23

Applications Information .............................................................. 25

Typical Operating Circuit ......................................................... 25

Evaluation Board ........................................................................ 26

Outline Dimensions ....................................................................... 27

Ordering Guide .......................................................................... 27

9/2012—Rev. B to Rev. C

Changes to Patent Footnote .............................................................1

Changes to Figure 46...................................................................... 17

Changes to Terminology Section ................................................. 19

Changes to Figure 53...................................................................... 25

Changes to Figure 55...................................................................... 27

Updated Outline Dimensions and changes to

Ordering Guide............................................................................... 29

2/2012—Rev. A to Rev. B

Deleted Linearity Compensation Section ......................................3

12/2011—Rev. 0 to Rev. A

Changes to Table 2.............................................................................3

Changes to Figure 48...................................................................... 18

Changes to DAC Register Section................................................ 22

Changes to Table 10 and Table 11 ................................................ 23

11/2011—Revision 0: Initial Version

Rev. F | Page 2 of 27

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