EVAL-AD5780SDZ データシートの表示（PDF） - Analog Devices

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EVAL-AD5780SDZ

System Ready, 18-Bit ±1 LSB INL, Voltage Output DAC

Analog Devices 

AD5780

SCLK

SYNC

SDIN

LDAC

VOUT

1

2

t6

t4

t1

t7

24

t3

t2

t5

t9

t8

DB23

t10

DB0

t11

t12

t13

Data Sheet

VOUT

t14

CLR

VOUT

RESET

VOUT

t15

t16

t21

t22

Figure 2. Write Mode Timing Diagram

SCLK

SYNC

SDIN

SDO

t17

1

2

t6

t4

t1

t7

24

t3

t2

t5

1

2

t17

t20

24

t5

t8

DB23

t9

INPUT WORD SPECIFIES

REGISTER TO BE READ

DB0

DB23

NOP CONDITION

t18

t19

DB0

REGISTER CONTENTS CLOCKED OUT

Figure 3. Readback Mode Timing Diagram

Rev. F | Page 6 of 27

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