EVAL-AD5781SDZ データシートの表示（PDF） - Analog Devices
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EVAL-AD5781SDZ Datasheet PDF : 27 Pages
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AD5781
Data Sheet
Parameter
Midscale Glitch Impulse
MSB Segment Glitch Impulse6
Output Enabled Glitch Impulse
Digital Feedthrough
DC Output Impedance (Normal Mode)
DC Output Impedance (Output
Clamped to Ground)
Spurious Free Dynamic Range
Total Harmonic Distortion
REFERENCE INPUTS3
VREFP Input Range
VREFN Input Range
DC Input Impedance
A, B Version1
Min
Typ Max
3.1
1.7
1.4
9.1
3.6
1.9
45
0.4
3.4
6
100
97
Unit
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
kΩ
kΩ
dB
dB
5
VSS + 2.5 V
5
6.6
VDD − 2.5 V V
0
kΩ
Input Capacitance
LOGIC INPUTS3
Input Current8
Input Low Voltage, VIL
Input High Voltage, VIH
Pin Capacitance
LOGIC OUTPUT (SDO)3
Output Low Voltage, VOL
Output High Voltage, VOH
High Impedance Leakage Current
High Impedance Output Capacitance
POWER REQUIREMENTS
VDD
VSS
VCC
IOVCC
IDD
ISS
ICC
IOICC
DC Power Supply Rejection Ratio3, 9
AC Power Supply Rejection Ratio3
15
−1
0.7 × IOVCC
5
IOVCC − 0.5 V
3
7.5
VDD − 33
2.7
1.71
4.2
4
600
52
±0.6
±0.6
95
95
pF
+1
µA
0.3 × IOVCC V
V
pF
0.4
V
±1
µA
pF
VSS + 33
−2.5
5.5
5.5
5.2
4.9
900
140
V
V
V
V
mA
mA
µA
µA
µV/V
µV/V
dB
dB
Test Conditions/Comments
VREFP = +10 V, VREFN = −10 V
VREFP = +10 V, VREFN = 0 V
VREFP = +5 V, VREFN = 0 V
VREFP = +10 V, VREFN = −10 V, see Figure 42
VREFP = 10 V, VREFN = 0 V, see Figure 43
VREFP = 5 V, VREFN = 0 V, see Figure 44
On removal of output ground clamp
1 kHz tone, 10 kHz sample rate
1 kHz tone, 10 kHz sample rate
VREFP, VREFN, code dependent,
typical at midscale code
VREFP, VREFN
IOVCC = 1.71 V to 5.5 V
IOVCC = 1.71 V to 5.5 V
IOVCC = 1.71 V to 5.5 V, sinking 1 mA
IOVCC = 1.71 V to 5.5 V, sourcing 1 mA
All digital inputs at DGND or IOVCC
IOVCC ≤ VCC
SDO disabled
VDD ± 10%, VSS = 15 V
VSS ± 10%, VDD = 15 V
VDD ± 200 mV, 50 Hz/60 Hz, VSS = −15 V
VSS ± 200 mV, 50 Hz/60 Hz, VDD = 15 V
1 Temperature range: −40°C to +125°C, typical conditions: TA = 25°C, VDD = +15 V, VSS = −15 V, VREFP = +10 V, VREFN = −10 V.
2 Performance characterized with AD8676BRZ voltage reference buffers and AD8675ARZ output buffer.
3 Linearity error refers to both INL error and DNL error; either parameter can be expected to drift by the amount specified after the length of time specified.
4 Valid for all voltage reference spans.
5 Guaranteed by design and characterization, not production tested.
6 The AD5781 is configured in the bias compensation mode with a low-pass RC filter on the output. R = 300 Ω, C = 143 pF (total capacitance seen by the output buffer,
lead capacitance, and so forth).
7 Includes noise contribution from AD8676BRZ voltage reference buffers.
8 Current flowing in an individual logic pin.
9 Includes PSRR of AD8676BRZ voltage reference buffers.
Rev. E | Page 4 of 27
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