EVAL-AD5930EB(Rev0) データシートの表示（PDF） - Analog Devices
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EVAL-AD5930EB
(Rev.:Rev0)
(Rev.:Rev0)
Analog Devices
EVAL-AD5930EB Datasheet PDF : 28 Pages
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AD5930
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
See Figure 4 to Figure 7. DVDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, all specifications TMIN to TMAX, unless otherwise noted.
Table 2.1
Parameter
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
Limit at TMIN, TMAX
20
8
8
25
10
10
5
10
5
3
2 x t1
0
10 x t1
8 x t1
2 x t1
2 x t1
2 x t1
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
ns typ
ns typ
ns typ
ns typ
ns max
Conditions/Comments
MCLK period
MCLK high duration
MCLK low duration
SCLK period
SCLK high time
SCLK low time
FSYNC to SCLK falling edge setup time
FSYNC to SCLK hold time
Data setup time
Data hold time
Minimum CTRL pulse width
CTRL rising edge to MCLK falling edge setup time
CTRL rising edge to IOUT/IOUTB delay (initial pulse, includes initialization)
CTRL rising edge to IOUT/IOUTB delay (initial pulse, includes initialization)
Frequency change to SYNC output, saw sweep, each frequency increment
Frequency change to SYNC output, saw sweep, end of sweep
Frequency change to SYNC output, triangle sweep, end of sweep
MCLK falling edge after 16th clock edge to MSB out
1 Guaranteed by design, not production tested.
t1
MCLK
t2
t3
Figure 3. Master Clock
SCLK
FSYNC
SDATA
t5
t4
t7
t6
t8
D15
D14
t10
t9
D2
D1
D0
Figure 4. Serial Timing
D15
D14
Rev. 0 | Page 6 of 28
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