AD6652BC データシートの表示（PDF） - Analog Devices
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AD6652BC Datasheet PDF : 76 Pages
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AD6652
GENERAL TIMING CHARACTERISTICS
All timing specifications valid over VDD range of 2.25 V to 2.75 V and VDDIO range of 3.0 V to 3.6 V.
CLOAD = 40 pF on all outputs, unless otherwise specified.
Table 6.
Parameter (Conditions)
CLK TIMING REQUIREMENTS
tCLK
CLK Period
tCLKL
CLK Width Low
tCLKH
CLK Width High
RESET TIMING REQUIREMENTS
tRESL
RESET Width Low
LEVEL INDICATOR OUTPUT SWITCHING CHARACTERISTICS
tDLI
↑CLK to LI (LIA, LIA; LIB, LIB) Output Delay Time
Temp
Full
Full
Full
Full
Full
Test Level Min
IV
15.4
IV
6.2
IV
6.2
IV
30.0
IV
3.3
Typ
tCLK/2
tCLK/2
Max Unit
ns
ns
ns
ns
10.0 ns
SYNC TIMING REQUIREMENTS
tSS
SYNC(A,B,C,D) to ↑CLK Setup Time
tHS
SYNC(A,B,C,D) to ↑CLK Hold Time
PARALLEL PORT TIMING REQUIREMENTS (MASTER MODE)
Switching Characteristics1
tDPOCLKL
↓CLK to ↑PCLK Delay (Divide-by-1)
tDPOCLKLL
↓CLK to ↑PCLK Delay (Divide-by-2, -4, or -8)
tDPREQ
↑PCLK to ↑PxREQ Delay
tDPP
↑PCLK to Px[15:0] Delay
Input Characteristics
tSPA
PxACK to ↓PCLK Setup Time
tHPA
PxACK to ↓PCLK Hold Time
PARALLEL PORT TIMING REQUIREMENTS (SLAVE MODE)
Switching Characteristics1
tPOCLK
PCLK Period
tPOCLKL
PCLK Low Period (when PCLK Divisor = 1)
tPOCLKH
PCLK High Period (when PCLK Divisor = 1)
tDPREQ
↑PCLK to ↑PxREQ Delay
tDPP
↑PCLK to Px[15:0] Delay
Input Characteristics
tSPA
PxACK to ↓PCLK Setup Time
tHPA
PxACK to ↓PCLK Hold Time
LINK PORT TIMING REQUIREMENTS
Switching Characteristics1
tRDLCLK
↑PCLK to ↑LxCLKOUT Delay
tFDLCLK
↓PCLK to ↓LxCLKOUT Delay
tRLCLKDAT
↑LCLKOUT to Lx[7:0] Delay
tFLCLKDAT
↓LCLKOUT to Lx[7:0] Delay
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
IV
IV
Full
IV
Full
IV
Full
IV
Full
IV
2.0
ns
1.0
ns
6.5
10.5 ns
8.3
14.6 ns
1.0
ns
0.0
ns
7.0
ns
−3.0
ns
12.5
ns
2.0
0.5 × tPOCLK
ns
2.0
0.5 × tPOCLK
ns
10.0 ns
11.0 ns
1.0
ns
1.0
ns
2.5
ns
0
ns
0
2.9
ns
0
2.2
ns
1 The timing parameters for Px[15:0], PxREQ, and PxACK apply for Port A and B (x stands for A or B).
Rev. 0 | Page 8 of 76
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