AD6653 データシートの表示（PDF） - Analog Devices
部品番号
コンポーネント説明
メーカー
AD6653 Datasheet PDF : 80 Pages
| |||
AD6653
TIMING SPECIFICATIONS
Table 5.
Parameter
SYNC TIMING REQUIREMENTS
tSSYNC
tHSYNC
SPI TIMING REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
tDIS_SDIO
SPORT TIMING REQUIREMENTS
tCSSCLK
tSSLKSDO
tSSCLKSDFS
Conditions
SYNC to the rising edge of CLK setup time
SYNC to the rising edge of CLK hold time
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Time required for the SDIO pin to switch from an input to an output
relative to the SCLK falling edge
Time required for the SDIO pin to switch from an output to an input
relative to the SCLK rising edge
Delay from rising edge of CLK+ to rising edge of SMI SCLK
Delay from rising edge of SMI SCLK to SMI SDO
Delay from rising edge of SMI SCLK to SMI SDFS
Min Typ Max Unit
0.24
ns
0.4
ns
2
ns
2
ns
40
ns
2
ns
2
ns
10
ns
10
ns
10
ns
10
ns
3.2 4.5
−0.4 0
−0.4 0
6.2 ns
+0.4 ns
+0.4 ns
Timing Diagrams
CLK+
DECIMATED
CMOS DATA
tPD
CHANNEL A/B
DATA BITS
tDCO
CHANNEL A/B
DATA BITS
CHANNEL A/B
DATA BITS
DECIMATED
FD DATA
CHANNEL A/B
FD BITS
CHANNEL A/B
FD BITS
CHANNEL A/B
FD BITS
CHANNEL A/B
FD BITS
CHANNEL A/B
FD BITS
CHANNEL A/B
FD BITS
DECIMATED
DCOA/DCOB
tS
tH
Figure 2. Decimated Noninterleaved CMOS Mode Data and Fast Detect Output Timing (Fast Detect Mode Select Bits = 000)
CLK+
tPD
tDCO
DECIMATED
CMOS DATA
CHANNEL A/B
DATA BITS
CHANNEL A/B
DATA BITS
CHANNEL A/B
DATA BITS
DECIMATED
FD DATA
DECIMATED
DCOA/DCOB
CHANNEL A/B
FD BITS
tS
tH
CHANNEL A/B
FD BITS
CHANNEL A/B
FD BITS
Figure 3. Decimated Noninterleaved CMOS Mode Data and Fast Detect Output Timing (Fast Detect Mode Select Bits = 001 Through Fast Detect Mode Select Bits = 100)
Rev. 0 | Page 10 of 80
Share Link: 