AD6655 データシートの表示（PDF） - Analog Devices

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AD6655

IF Diversity Receiver

Analog Devices 

AD6655

ADC DC SPECIFICATIONS—AD6655BCPZ-125/AD6655BCPZ-150

AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference,

DCS enabled, unless otherwise noted.

Table 2.

Parameter

RESOLUTION

ACCURACY

No Missing Codes

Offset Error

Gain Error

MATCHING CHARACTERISTIC

Offset Error

Gain Error

TEMPERATURE DRIFT

Offset Error

Gain Error

INTERNAL VOLTAGE REFERENCE

Output Voltage Error (1 V Mode)

Load Regulation @ 1.0 mA

INPUT-REFERRED NOISE

VREF = 1.0 V

ANALOG INPUT

Input Span, VREF = 1.0 V

Input Capacitance1

VREF INPUT RESISTANCE

POWER SUPPLIES

Supply Voltage

AVDD, DVDD

DRVDD (CMOS Mode)

DRVDD (LVDS Mode)

Supply Current

IAVDD2, 3

IDVDD2, 3

IDRVDD2 (3.3 V CMOS)

IDRVDD2 (1.8 V CMOS)

IDRVDD2 (1.8 V LVDS)

POWER CONSUMPTION

DC Input

Sine Wave Input2 (DRVDD = 1.8 V)

Sine Wave Input2 (DRVDD = 3.3 V)

Standby Power4

Power-down Power

Temperature

Full

Full

Full

Full

25°C

25°C

Full

Full

Full

Full

25°C

Full

Full

Full

AD6655BCPZ-125

Min

Typ

Max

14

Guaranteed

±0.3

±0.6

−4.7

−2.7

−0.8

±0.3

±0.7

±0.1

±0.7

±15

±95

±5

±18

7

0.85

2

8

6

Full

1.7

1.8

1.9

Full

1.7

1.8

3.6

Full

1.7

1.8

1.9

Full

390

705

Full

270

Full

26

Full

13

Full

57

Full

770

810

Full

1215

Full

1275

Full

77

Full

2.5

8

AD6655BCPZ-150

Min Typ

Max

14

Guaranteed

±0.2

±0.6

−5.1 −3.2

−1.0

±0.2

±0.7

±0.2

±0.8

±15

±95

±5

±18

7

0.85

2

8

6

1.7 1.8

1.9

1.7 1.8

3.6

1.7 1.8

1.9

440

805

320

28

17

57

870

920

1395

1450

77

2.5

8

Unit

Bits

% FSR

% FSR

% FSR

% FSR

ppm/°C

ppm/°C

mV

mV

LSB rms

V p-p

pF

kΩ

V

V

V

mA

mA

mA

mA

mA

mW

mW

mW

mW

mW

1 Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 11 for the equivalent analog input structure.

2 Measured with a 9.7 MHz, full-scale sine wave input, NCO enabled with a frequency of 13 MHz, FIR filter enabled and the fS/8 output mix enabled with approximately

5 pF loading on each output bit.

3 The maximum limit applies to the combination of IAVDD and IDVDD currents.

4 Standby power is measured with a dc input, the CLK pin inactive (set to AVDD or AGND).

Rev. 0 | Page 6 of 84

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