AD7171 データシートの表示（PDF） - Analog Devices
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AD7171 Datasheet PDF : 16 Pages
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Data Sheet
AD7171
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.25 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = VDD, unless otherwise noted.
Table 3.
Parameter1, 2
READ
t1
t2
t33
t4
RESET
t5
t6
Limit at TMIN, TMAX
100
100
0
60
80
10
100
25
Unit
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ms typ
Test Conditions/Comments
SCLK high pulse width
SCLK low pulse width
SCLK active edge to data valid delay4
VDD = 4.75 V to 5.25 V
VDD = 2.7 V to 3.6 V
SCLK inactive edge to DOUT/RDY high
PDRST low pulse width
PDRST high to data valid delay
1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2 See Figure 3.
3 These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.
4 SCLK active edge is the falling edge of SCLK.
Timing Diagrams
ISINK (1.6mA WITH VDD = 5V,
100µA WITH VDD = 3V)
TO
OUTPUT
PIN
50pF
1.6V
ISOURCE (200µA WITH VDD = 5V,
100µA WITH VDD = 3V)
Figure 2. Load Circuit for Timing Characterization
DOUT/RDY (O)
SCLK (I)
MSB
t3
t1
LSB
t4
t2
I = INPUT, O = OUTPUT
Figure 3. Read Cycle Timing Diagram
PDRST (I)
t5
t6
DOUT/RDY (O)
I = INPUT, O = OUTPUT
Figure 4. Resetting the AD7171
Rev. C | Page 5 of 16
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