AD7225(RevB) データシートの表示（PDF） - Analog Devices
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AD7225 Datasheet PDF : 12 Pages
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MICROPROCESSOR INTERFACE
A15
A8
8085A/
8088
WR
ALE
AD7
AD0
ADDRESS BUS
ADDRESS
DECODE
LATCH
EN
A0
A1
LDAC
AD7225*
WR
DB7
DB0
ADDRESS DATA BUS
*LINEAR CIRCUITRY OMITTED FOR CLARITY
Figure 22. AD7225 to 8085A/8088 Interface,
Double-Buffered Mode
A15
A0
6809/
6502
R/W
E OR φ2
D7
D0
ADDRESS BUS
ADDRESS
DECODE
EN
A0
A1
LDAC
AD7225*
WR
DB7
DB0
DATA BUS
*LINEAR CIRCUITRY OMITTED FOR CLARITY
Figure 23. AD7225 to 6809/6502 Interface,
Single-Buffered Mode
A15
A8
Z-80
MREQ
WR
D7
D0
ADDRESS BUS
ADDRESS
DECODE
EN
A0
A1
LDAC
AD7225*
WR
DB7
DB0
DATA BUS
*LINEAR CIRCUITRY OMITTED FOR CLARITY
Figure 24. AD7225 to Z-80 Interface,
Double-Buffered Mode
AD7225
A23
A1
68008
AS
R/W
DTACK
D7
D0
ADDRESS BUS
ADDRESS
DECODE
EN
A0
A1
AD7225*
WR
LDAC
DB7
DB0
DATA BUS
*LINEAR CIRCUITRY OMITTED FOR CLARITY
Figure 25. AD7225 to 68008 Interface,
Single-Buffered Mode
VSS GENERATION
Operating the AD7225 from dual supplies results in enhanced
performance over single supply operation on a number of pa-
rameters as previously outlined. Some applications may require
this enhanced performance, but may only have a single power
supply rail available. The circuit of Figure 26 shows a method of
generating a negative voltage using one CD4049, operated from
a VDD of +15 V. Two inverters of the hex inverter chip are used
as an oscillator. The other four inverters are in parallel and used
as buffers for higher output current. The square-wave output is
level translated to a negative-going signal, then rectified and fil-
tered. The circuit configuration shown will provide an output
voltage of –5.1 V for current loadings in the range 0.5 mA to
9 mA. This will satisfy the AD7225 ISS requirement over the
commercial operating temperature range.
1/6
1/6
CD4049AE CD4049AE
510k
5.1k
0.02µF
1/6
CD4049AE
1/6
CD4049AE
1/6
CD4049AE
1/6
CD4049AE
+
47µF
510Ω
1N4001
1N4001
47µF
+
–VOUT
5V1
Figure 26. VSS Generation Circuit
REV. B
–11–
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