AD7233(RevA) データシートの表示（PDF） - Analog Devices
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AD7233 Datasheet PDF : 8 Pages
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There are two ways in which the DAC latch and hence the ana-
log output may be updated. The status of the LDAC input is
examined after SYNC is taken low. Depending on its status, one
of two update modes is selected.
If LDAC = 0 then the automatic update mode is selected. In
this mode the DAC latch and analog output are updated auto-
matically when the last bit in the serial data stream is clocked in.
The update thus takes place on the sixteenth falling SCLK edge.
AD7233
If LDAC = 1 then the automatic update is disabled and the
DAC latch is updated by taking LDAC low any time after the
16-bit data transfer is complete. The update now occurs on the
falling edge of LDAC. This facility is useful for simultaneous
update in multi-DAC systems. Note that the LDAC input must
be taken back high again before the next data transfer is initiated.
SYNC
SCLK
SDIN
LDAC
SCLK
SYNC
SDIN
LDAC
RESET
–16
COUNTER/
DECODER
GATING
SIGNAL
GATED
SCLK
INPUT SHIFT REGISTER (16 BITS)
AUTO-UPDATE
CIRCUITRY
DAC LATCH (12 BITS)
Figure 2. Simplified Loading Structure
t1
t2
t4
t5
DB15
DB14
DB13
DB12
DON'T CARE DON'T CARE DON'T CARE DON'T CARE
DB11
MSB
t3
DB1
DB0
LSB
t6
t7
t8
Figure 3. Timing Diagram
REV. A
–5–
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