AD7233(RevA) データシートの表示（PDF） - Analog Devices
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AD7233 Datasheet PDF : 8 Pages
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AD7233–Typical Performance Graphs
0.50
0.40
0.30
0.20
TA = +25 C
0.10
0
10.5 11
12
13
14
15
16
VDD /VSS – Volts
Linearity vs. Power Supply Voltage
100
OUTPUT WITH ALL
90
0s ON DAC
DECOUPLING
80
OUTPUT WITH ALL
70
1s ON DAC
NO DECOUPLING
DECOUPLING
60
50
40
NO DECOUPLING
30
20
10 VDD = +15V WITH
100mV p–p SIGNAL
0
10
100
1k
10k
FREQUENCY – Hz
100k
* POWER SUPPLY DECOUPLING CAPACITORS
ARE 10µF AND 0.1µF.
Power Supply Rejection Ratio
vs. Frequency
500
VDD = +15V
200
VSS = – 15V
TA = +25 C
100
50
20
OUTPUT WITH ALL
0s ON DAC
0
50 100 200 500 1k 2k 5k 10k 20k 50k 100k
FREQUENCY – Hz
Noise Spectral Density
vs. Frequency
APPLYING THE AD7233
Bipolar (؎5 V) Configuration
The AD7233 provides an output voltage range from –5 V to
+5 V without any external components. This configuration is
shown in Figure 4. The data format is two's complement. The
output code table is shown in Table I. If offset binary coding is
required, then this can be done by inverting the MSB in soft-
ware before the data is loaded to the AD7233.
AD7233
+12V TO +15V
VDD
2R
2R
12-BIT
+5V
DAC
VOUT
Table I. AD7233 Bipolar Code Table
Input Data Word
MSB LSB
XXXX 0111 1111 1111
XXXX 0000 0000 0001
XXXX 0000 0000 0000
XXXX 1111 1111 1111
XXXX 1000 0000 0001
XXXX 1000 0000 0000
X = Don’t Care
Note: 1 LSB = 5 V/2048 ≈ 2.4 mV
Analog Output, VOUT
+5 V • (2047/2048)
+5 V • (1/2048)
0V
–5 V • (1/2048)
–5 V • (2047/2048)
–5 V • (2048/2048) = –5 V
VSS
–12V TO –15V
GND
Figure 4. Circuit Configuration
Power Supply Decoupling
To achieve optimum performance when using the AD7233, the
VDD and VSS lines should each be decoupled to GND using
0.1 µF capacitors. In very noisy environments it is recom-
mended that 10 µF capacitors be connected in parallel with the
0.1 µF capacitors.
–6–
REV. A
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