AD7233(RevA) データシートの表示（PDF） - Analog Devices
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AD7233 Datasheet PDF : 8 Pages
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AD7233
AD7233-68HC11 Interface
Figure 8 shows a serial interface between the AD7233 and the
68HC11 microcontroller. SCK of the 68HC11 drives SCLK of
the AD7233 while the MOSI output drives the serial data line.
The SYNC signal is derived from a port line (PC7 shown).
For correct operation of this interface, the 68HC11 should be
configured such that its CPOL bit is a 0 and its CPHA bit is a
1. When data is to be transmitted to the part, PC7 is taken low.
When the 68HC11 is configured like this, data on MOSI is
valid on the falling edge of SCK. The 68HC11 transmits its se-
rial data in 8-bit bytes with only eight falling clock edges occur-
ring in the transmit cycle. To load data to the AD7233, PC7 is
kept low after the first eight bits are transferred and a second
byte of data is then transferred serially to the AD7233. When
the second serial transfer is complete, the PC7 line is taken
high. Figure 8 shows the LDAC input of the AD7233 hard-
wired low. As a result, the DAC latch and the analog output of
the DAC will be updated on the sixteenth falling edge of SCK
after the respective SYNC signal has gone low. Alternatively,
the scheme used in previous interfaces, whereby the LDAC in-
put is driven from a timer, can be used.
68HC11*
LDAC
AD7233*
PC7
SYNC
SCK
MOSI
SCLK
SDIN
* ADDITIONAL PINS OMITTED FOR CLARITY
Figure 8. AD7233 to 68HC11 Interface
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Plastic DIP (N-8) Package
8
5
0.280 (7.11)
0.240 (6.10)
1
4
0.210
(5.33)
MAX
0.022 (0.558)
0.014 (0.356)
0.430 (10.92)
0.348 (8.84)
0.060 (1.52)
0.015 (0.38)
0.150
(3.81)
MIN
0.100 BSC
(2.54 BSC)
0.70 (1.77)
0.045 (1.15)
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95) MAX
–8–
REV. A
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