EVAL-CEDZ データシートの表示（PDF） - Analog Devices

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EVAL-CEDZ

1 MSPS, 14-Bit, Simultaneous Sampling SAR ADC with PGA and Four Comparators

Analog Devices 

AD7264

SPECIFICATIONS

AVCC = 4.75 V to 5.25 V, CA_CBVCC = CC_CDVCC = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, fS = 1 MSPS and fSCLK = 34 MHz for

the AD7264, fS = 500 kSPS and fSCLK = 20 MHz for the AD7264-5, VREF = 2.5 V internal/external; TA = −40°C to +105°C, unless otherwise

noted.

Table 1.

Parameter

Min

DYNAMIC PERFORMANCE1

Signal-to-Noise Ratio (SNR)2

76

Signal-to-(Noise + Distortion) Ratio

74

(SINAD)2

Total Harmonic Distortion (THD)2

Spurious-Free Dynamic Range (SFDR)

Common-Mode Rejection Ratio (CMRR)

Typ

Max

78

77

−85

−77

−97

−76

ADC-to-ADC Isolation2

Bandwidth3

DC ACCURACY

Resolution

Integral Nonlinearity2

Differential Nonlinearity2

Positive Full-Scale Error2

Positive Full-Scale Error Match2

Zero Code Error2

Zero Code Error Match2

Negative Full-Scale Error2

Negative Full-Scale Error Match2

Zero Code Error Drift

ANALOG INPUT

Input Voltage Range, VIN+ and VIN−

Common-Mode Voltage Range, VCM

DC Leakage Current

Input Capacitance3

Input Impedance3

REFERENCE INPUT/OUTPUT

Reference Output Voltage5

Reference Input Voltage

DC Leakage Current

Input Capacitance3

VREFA, VREFB Output Impedance3

Reference Temperature Coefficient

VREF Noise3

−90

1.2

1.7

±1.5

±0.5

±0.122

±0.018

±0.061

±0.092

±0.012

±0.061

±0.122

±0.018

±0.061

2.5

14

±3

±0.99

±0.305

±0.244

±0.305

VCM

±

2

VREF

× Gain

VCM − 100 mV

VCM + 100 mV

(VCC/2) − 0.4

(VCC/2) − 0.4

(VCC/2) − 0.6

±0.001

5

1

(VCC/2) + 0.2

(VCC/2) + 0.4

(VCC/2) + 0.8

±1

2.495

2.5

2.505

2.5

±0.3

±1

20

4

20

20

Unit

dB

dB

dB

dB

dB

dB

MHz

MHz

Bits

LSB

LSB

% FSR

% FSR

% FSR

% FSR

% FSR

% FSR

% FSR

% FSR

% FSR

μV/°C

V

V

V

V

V

μA

pF

GΩ

V

V

μA

pF

Ω

ppm/°C

μV rms

Test Conditions/Comments

fIN = 100 kHz sine wave

PGA gain setting = 2

For PGA gain setting = 2, ripple

frequency of 50 Hz/60 Hz; see

Figure 17 and Figure 18

@ −3 dB; PGA gain setting = 128

@ −3 dB; PGA gain setting = 2

Guaranteed no missed codes to 14 bits

Precalibration

Postcalibration

Precalibration

Postcalibration

Precalibration

Postcalibration

VCM = AVCC/2; PGA gain setting ≥ 2

VCM = 2 V; PGA gain setting = 1;

see Figure 194

VCM = AVCC/2; PGA gain setting = 2

VCM = AVCC/2; 3 ≤ PGA gain setting ≤ 32

VCM = AVCC/2; PGA gain setting ≥ 48

2.5 V ± 5 mV max @ 25°C

External reference applied to

Pin VREFA/Pin VREFB

Rev. A | Page 3 of 32

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