AD7265 データシートの表示（PDF） - Analog Devices
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AD7265 Datasheet PDF : 29 Pages
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AD7265
TIMING SPECIFICATIONS
AVDD = DVDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, internal/external reference = 2.5 V, TA = TMAX to TMIN, unless otherwise noted1.
Table 2.
Parameter
fSCLK 2
tCONVERT
tQUIET
t2
t3
t4 3
t5
t6
t7
t8
t9
t10
Limit at TMIN, TMAX
1
4
16
14 × tSCLK
875
30
15/20
20/30
15
36
27
0.45 tSCLK
0.45 tSCLK
10
5
15
30
5
50
Unit
MHz min
MHz min
MHz max
ns max
ns max
ns min
ns min
ns min
ns max
ns max
ns max
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns max
Description
TA = −40°C to +85°C
TA > 85°C to 125°C
tSCLK = 1/fSCLK
fSCLK = 16 MHz
Minimum time between end of serial read and next falling edge of CS
VDD = 5 V/3 V, CS to SCLK setup time, TA = −40°C to +85°C
VDD = 5 V/3 V, CS to SCLK setup time, TA > 85°C to 125°C
Delay from CS until DOUTA and DOUTB are three-state disabled
Data access time after SCLK falling edge, VDD = 3 V
Data access time after SCLK falling edge, VDD = 5 V
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time, VDD = 3 V
SCLK to data valid hold time, VDD = 5 V
CS rising edge to DOUTA, DOUTB, high impedance
CS rising edge to falling edge pulse width
SCLK falling edge to DOUTA, DOUTB, high impedance
SCLK falling edge to DOUTA, DOUTB, high impedance
1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See the Serial
Interface section and Figure 41 and Figure 42.
2 Minimum SCLK for specified performance; with slower SCLK frequencies, performance specifications apply typically.
3 The time required for the output to cross 0.4 V or 2.4 V.
Rev. A | Page 5 of 28
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