AD7280 データシートの表示（PDF） - Analog Devices
部品番号
コンポーネント説明
メーカー
AD7280 Datasheet PDF : 33 Pages
| |||
AD7280
Preliminary Technical Data
Parameter1
Min
Typ
Max
Unit
Test Conditions/Comments
POWER DISSIPATION
During Conversion
300
mW
VDD = 30 V
Full Powerdown Mode
120
µW
VDD = 30 V
1 Temperature range is −40°C to +105°C.
2 For dc accuracy specifications, the LSB size for cell voltage measurements is (2VREF-1V)/4096, the LSB size for temperature measurements is 2VREF/4096.
3 ADC Unadjusted Error includes the INL of the ADC and the Gain and Offset Errors of the Vin0 to Vin6 input channels.
4 Total Unadjusted Error includes the INL of the ADC and the Gain and Offset Errors of the Vin0 to Vin6 input channels as well as the temperature coefficient of the 2.5V reference.
5 ADC Unadjusted Error includes the INL of the ADC and the Gain and Offset Errors of the VT input channels.
6 Total Unadjusted Error includes the INL of the ADC and the Gain and Offset Errors of the VT input channels as well as the temperature coefficient of the 2.5V reference.
7 This spec outlines the regulator output current which is available for external use, that is, it does not include the regulator current already being used by the AD7280.
8 CB output can be set to 0V or 5V with respect to negative terminal of cell being balanced.
9 CB1 output ramp up time is defined from the rising edge of the CS command until the CB output exceeds 4V with respect to negative terminal of cell being balanced.
10 CB1 output ramp down time is defined from the falling edge of the CS command until the CB output falls below 50mV with respect to negative terminal of cell being
balanced. This specification is defined from the falling edge of CS as any CB outputs which on are switched off for the duration of a CS low pulse and will be switched
back on following the rising edge of that CS pulse.
11 CB2 to CB6 output ramp up time is defined from the rising edge of the CS command until the CB output exceeds 4V with respect to negative terminal of cell being
balanced.
12 CB2 to CB6 output ramp down time is defined from the falling edge of the CS command until the CB output falls below 50mV with respect to negative terminal of cell
being balanced. This specification is defined from the falling edge of CS as any CB outputs which on are switched off for the duration of a CS low pulse and will be
switched back on following the rising edge of that CS pulse.
TIMING SPECIFICATIONS
VDD = 7.5 V to 30 V, VSS = 0 V, DVCC = AVCC = VREG, VDRIVE = 2.7 V to 5.25 V, TA = -40oC to 105oC, unless otherwise noted.1
Table 2.
Parameter
tCONV
tDELAY
Limit at TMIN, TMAX
2.7 V ≤ VDRIVE < 4.75 V 4.75 V ≤ VDRIVE ≤ 5.25 V
610
610
50
50
Unit
ns max
ns max
fSCLK
10
10
1
1
tQUIET
200
200
kHz min
MHz max
ns min
t1
10
10
t2
10
10
t3
10
10
ns min
ns min
ns max
t4
5
t5
3
t62
20
t7
7
t8
0.3 × tSCLK
t9
0.3 × tSCLK
t10
10
t11
10
5
3
14
7
0.3 × tSCLK
0.3 × tSCLK
10
10
ns min
ns min
ns max
ns min
ns min
ns min
ns min
ns max
Test Conditions/Comments
ADC Conversion time
Propogation delay between adjacent parts on the Daisy
Chain
Frequency of serial read clock
Minimum quiet time required between the end of serial
read and the start of the next conversion
Minimum CONVST low pulse
CS falling edge to SCLK rising edge
Delay from CS falling edge until SDO is three-state
disabled
SDI setup time prior to SCLK falling edge
SDI hold time after SCLK falling edge
Data access time after SCLK falling edge
SCLK to data valid hold time
SCLK high pulse width
SCLK low pulse width
CS rising edge to SCLK rising edge
CS rising edge to SDO high impedance
1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
All timing specifications given are with a 25 pF load capacitance.
2 The time required for the output to cross 0.4 V or 2.4 V.
Rev. PrD | Page 4 of 33
Share Link: 