AD7303BRZ-REEL7 データシートの表示（PDF） - Analog Devices
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AD7303BRZ-REEL7 Datasheet PDF : 16 Pages
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SERIAL INTERFACE
The AD7303 contains a versatile 3-wire serial interface that is
compatible with SPI, QSPI and Microwire interface stan-
dards as well as a host of digital signal processors. An active
low SYNC enables the shift register to receive data from the
serial data input DIN. Data is clocked into the shift register on
the rising edge of the serial clock. The serial clock frequency
can be as high as 30 MHz. This shift register is 16 bits wide as
shown in Figures 23 and 24. The first eight bits are control bits
and the second eight bits are data bits for the DACs. Each
transfer must consist of a 16-bit transfer. Data is sent MSB first
and can be transmitted in one 16-bit write or two 8-bit writes.
SPI and Microwire interfaces output data in 8-bit bytes and
thus require two 8-bit transfers. In this case the SYNC input to
the DAC should remain low until all sixteen bits have been
transferred to the shift register. QSPI interfaces can be pro-
AD7303
grammed to transfer data in 16-bit words. After clocking all six-
teen bits to the shift register, the rising edge of SYNC executes
the programmed function. The DACs are double buffered
which allows their outputs to be simultaneously updated.
INPUT SHIFT REGISTER DESCRIPTION
The input shift register is 16 bits wide. The first eight bits con-
sist of control bits and the last eight bits are data bits. Figure 23
shows a block diagram of the logic interface on the AD7303
DAC. The seven bits in the control word are taken from the in-
put shift register to a latch sequencer that decodes this data and
provides output signals that control the data transfers to the in-
put and data registers of the selected DAC, as well as output
updating and various power-down features associated with the
control section. A description of all bits contained in the input
shift register is given below.
MSB INT/EXT
X
LDAC
PDB
PDA
A/B
CR1
CR0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
LSB DB0
SYNC
7
8
8
8
LATCH
SEQUENCER
LATCH & CLK
DRIVERS
16
CLOCK BUS
INPUT
8
REGISTER
DAC A POWER-DOWN
DAC B POWER-DOWN
BANDGAP POWER-DOWN
REF
SELECTOR
INT
REFERENCE
CURRENT
SWITCH
BANDGAP
BIAS GEN
REF
RESISTOR
SWITCH
30
8 TO 32
DECODER
DAC
30
REGISTER
DAC A
INPUT
8
REGISTER
8 TO 32
30
DECODER
30
DAC
REGISTER
DAC B
SYNC
SCLK
DIN
Figure 23. Logic Interface on the AD7303
DAC A BIAS
DAC B BIAS
VOUT A
VOUT B
REV. 0
–9–
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