AD7475BRM-REEL データシートの表示（PDF） - Analog Devices
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AD7475BRM-REEL Datasheet PDF : 24 Pages
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AD7475/AD7495
TIMING SPECIFICATIONS1
VDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, REF IN = 2.5 V (AD7475), TA = TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
fSCLK 2
tCONVERT
tQUIET
t2
t3 3
t4
t5
t6
t7
t8 4
t9
tPOWER-UP
Limit at TMIN, TMAX
10
20
16 × tSCLK
800
100
10
22
40
0.4 tSCLK
0.4 tSCLK
10
10
45
20
20
650
Unit
kHz min
MHz max
ns max
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
ns max
μs max
μs max
Description
tSCLK = 1/fSCLK
fSCLK = 20 MHz
Minimum quiet time required between conversions
CS to SCLK setup time
Delay from CS until SDATA three-state disabled
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time
SCLK falling edge to SDATA high impedance
SCLK falling edge to SDATA high impedance
CS rising edge to SDATA high impedance
Power-up time from full power-down (AD7475)
Power-up time from full power-down (AD7495)
1 Guaranteed by initial characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
2 Mark/space ratio for the SCLK input is 40/60 to 60/40.
3 Measured with the load circuit of Figure 4 and defined as the time required for the output to cross 0.8 V or 2.0 V.
4 t8 and t9 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 4. The measured number is
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times, t8 and t9, quoted in the timing characteristics are
the true bus relinquish times of the part and are independent of the bus loading.
Rev. B | Page 7 of 24
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