AD7490BRU(RevA) データシートの表示（PDF） - Analog Devices
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AD7490BRU Datasheet PDF : 24 Pages
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AD7490
power consumption is of concern, the power-down modes should
be used between conversions or bursts of several conversions to
improve power performance. (See Modes of Operation section.)
0.1F 10F
5V
SUPPLY
SERIAL
INTERFACE
0V TO REFIN
VIN 0 VDD
•
•
VIN 15
AD7490
AGND REFIN
SCLK
DOUT
CS
VDRIVE DIN
C/P
0.1F
2.5V
AD780
0.1F 10F
3V
SUPPLY
ALL UNUSED INPUT CHANNELS SHOULD BE CONNECTED TO GND
Figure 11. Typical Connection Diagram
Analog Input
Any one of 16 analog input channels may be selected for conversion
by programming the multiplexer with the address bits ADD3–ADD0
in the Control Register. The channel configurations are shown in
Table II. The AD7490 may also be configured to automatically
cycle through a number of channels as selected. The sequencer
feature is accessed via the SEQ and SHADOW Bits in the Control
Register (see Table IV). The AD7490 can be programmed to
continuously convert on a selection of channels in ascending order.
The analog input channels to be converted on are selected through
programming the relevant bits in the Shadow Register (see Table V).
The next serial transfer will then act on the sequence programmed
by executing a conversion on the lowest channel in the selection.
The next serial transfer will result in a conversion on the next
highest channel in the sequence and so on. It is not necessary to
write to the Control Register once a sequencer operation has
been initiated. The WRITE Bit must be set to zero or the DIN
line tied low to ensure the Control Register is not accidently
overwritten, or the sequence operation interrupted. If the
Control Register is written to at any time during the sequence, then
it must be ensured that the SEQ and Shadow Bits are set to 1, 0
to avoid interrupting the automatic conversion sequence. This
pattern will continue until such time as the AD7490 is written to
and the SEQ and Shadow Bits are configured with any bit combi-
nation except 1, 0. On completion of the sequence, the AD7490
sequencer will return to the first selected channel in the Shadow
Register and commence the sequence again if uninterrupted.
Rather than selecting a particular sequence of channels, a number
of consecutive channels beginning with channel 0 may also be
programmed via the Control Register alone without needing to
write to the Shadow Register. This is possible if the SEQ and
Shadow Bits are set to 1, 1. The channel address bits ADD3
through ADD0 will then determine the final channel in the consecu-
tive sequence. The next conversion will be on Channel 0, then
Channel 1 and so on until the channel selected via the address
bits ADD3 through ADD0 is reached. The cycle will begin
again on the next serial transfer provided the WRITE Bit is set
to low or, if high, that the SEQ and Shadow Bits are set to 1, 0;
then the ADC will continue its preprogrammed automatic se-
quence uninterrupted. Regardless of which channel selection
method is used, the 16-bit word output from the AD7490 during
each conversion will always contain the channel address that the
conversion result corresponds to followed by the 12-bit conver-
sion result (see Serial Interface section).
Digital Inputs
The digital inputs applied to the AD7490 are not limited by the
maximum ratings that limit the analog inputs. Instead, the digi-
tal inputs applied can go to 7 V and are not restricted by the
VDD + 0.3 V limit as on the analog inputs.
Another advantage of SCLK, DIN, and CS not being restricted
by the VDD + 0.3 V limit is the fact that power supply sequencing
issues are avoided. If CS, DIN, or SCLK are applied before VDD,
then there is no risk of latch-up as there would be on the analog
inputs if a signal greater than 0.3 V was applied prior to VDD.
VDRIVE
The AD7490 also has the VDRIVE feature. VDRIVE controls the voltage
at which the serial interface operates. VDRIVE allows the ADC to
easily interface to both 3 V and 5 V processors. For example, if
the AD7490 were operated with a VDD of 5 V, the VDRIVE Pin
could be powered from a 3 V supply. The AD7490 has better
dynamic performance with a VDD of 5 V while still being able to
interface to 3 V processors. Care should be taken to ensure VDRIVE
does not exceed VDD by more than 0.3 V. (See Absolute Maximum
Ratings section.)
Reference Section
An external reference source should be used to supply the 2.5 V
reference to the AD7490. Errors in the reference source will result
in gain errors in the AD7490 transfer function and will add to the
specified full scale errors of the part. A capacitor of at least 0.1 µF
should be placed on the REFIN Pin. Suitable reference sources
for the AD7490 include the AD780, REF193, and the AD1852.
If 2.5 V is applied to the REFIN Pin, the analog input range can
either be 0 V to 2.5 V or 0 V to 5 V, depending on the RANGE
Bit in the Control Register.
MODES OF OPERATION
The AD7490 has a number of different modes of operation. These
modes are designed to provide flexible power management options.
These options can be chosen to optimize the power dissipation/
throughput rate ratio for differing application requirements. The
mode of operation of the AD7490 is controlled by the power
management bits, PM1 and PM0, in the Control Register, as
detailed in Table III. When power supplies are first applied to the
AD7490, care should be taken to ensure the part is placed in the
required mode of operation (see Powering Up the AD7490 section.)
–14–
REV. A
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