AD7490BRU(RevA) データシートの表示（PDF） - Analog Devices

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AD7490BRU
(Rev.:RevA)

16-Channel, 1 MSPS, 12-Bit ADC with Sequencer in 28-Lead TSSOP

Analog Devices 

AD7490

AD7490 in this mode. In Shutdown Mode, all internal circuitry on

the AD7490 is powered down. The part retains information in

the Control Register during shutdown. The AD7490 remains in

shutdown until the next CS falling edge it receives. On this CS

falling edge, the track and hold that was in hold while the part was

in shutdown will return to track. Wake-up time from auto shut-

down is 1 µs, and the user should ensure that 1 µs has elapsed

before attempting a valid conversion. When running the AD7490

with a 20 MHz clock, one dummy cycle of 16 ϫ SCLKs should

be sufficient to ensure the part is fully powered up. During this

dummy cycle, the contents of the Control Register should remain

unchanged; therefore the WRITE Bit should be 0 on the DIN line.

This dummy cycle effectively halves the throughput rate of the part,

with every other conversion result being valid. In this mode, the

power consumption of the part is greatly reduced with the part

entering shutdown at the end of each conversion. When the Control

Register is programmed to move into auto shutdown, it does so

at the end of the conversion. The user can move the ADC in and

out of the low power state by controlling the CS signal.

Auto Standby (PM1 = PM0 = 0)

In this mode, the AD7490 automatically enters Standby Mode at

the end of each conversion when the Control Register is updated.

Figure 15 shows the general diagram of the operation of the

AD7490 in this mode. When the part is in standby, portions of the

AD7490 are power-down but the on-chip bias generator remains

powered up. The part retains information in the Control Register

during standby. The AD7490 remains in standby until it receives

the next CS falling edge. On this CS falling edge, the track and

hold that was in hold while the part was in standby will return to

track. Wake-up time from standby is 1 µs; the user should ensure

that 1 µs has elapsed before attempting a valid conversion on the

part in this mode. When running the AD7490 with a 20 MHz

clock, one dummy cycle of 16 ϫ SCLKs should be sufficient to

ensure the part is fully powered up. During this dummy cycle, the

contents of the Control Register should remain unchanged,

therefore the WRITE Bit should be set to 0 on the DIN line. This

dummy cycle effectively halves the throughput rate of the part

with every other conversion result being valid. In this mode, the

power consumption of the part is greatly reduced with the part

entering standby at the end of each conversion. When the Control

Register is programmed to move into Auto Standby, it does so at

the end of the conversion. The user can move the ADC in and out

of the low power state by controlling the CS signal.

Powering Up the AD7490

When supplies are first applied to the AD7490, the ADC may

power up in any of the operating modes of the part. To ensure the

part is placed into the required operating mode, the user should

perform a dummy cycle operation as outlined in Figure 16.

The three dummy conversion operations outlined in Figure 16 must

be performed to place the part into either of the auto modes. The

first two conversions of this dummy cycle operation are performed

with the DIN line tied HIGH, and for the third conversion of the

dummy cycle operation, the user should write the desired control

register configuration to the AD7490 in order to place the part

into the required Auto Mode. On the third CS rising edge after the

CS

1

SCLK

PART ENTERS

STANDBY ON CS

RISING EDGE AS

PM1 ؍0, PM0 ؍0

PART BEGINS

TO POWER

UP ON CS

FALLING EDGE

12

16

DUMMY CONVERSION

1

12

16

PART IS FULLY

POWERED UP

1

PART ENTERS

STANDBY ON CS

RISING EDGE AS

PM1 ؍0, PM0 ؍0

12

16

DOUT

CHANNEL IDENTIFIER BITS + CONVERSION RESULT

INVALID DATA

CHANNEL IDENTIFIER BITS + CONVERSION RESULT

DIN

CS

SCLK

DATA IN TO CONTROL/SHADOW REGISTER

DATA IN TO CONTROL/SHADOW REGISTER

CONTROL REGISTER IS LOADED ON THE

FIRST 12 CLOCKS, PM1 ؍0, PM0 ؍0

CONTROL REGISTER SHOULD REMAIN

UNCHANGED, WRITE BIT ؍0

TO KEEP PART IN THIS MODE, LOAD PM1 ؍0,

PM0 ؍0 IN CONTROL REGISTER

Figure 15. Auto Standby Mode Operation

CORRECT VALUE IN CONTROL

REGISTER VALID DATA FROM

NEXT CONVERSION USER CAN

WRITE TO SHADOW REGISTER

IN NEXT CONVERSION

DUMMY CONVERSION

DUMMY CONVERSION

1

12

16

1

12

16

1

12

16

DOUT

INVALID DATA

INVALID DATA

INVALID DATA

DIN

DATA IN TO CONTROL

KEEP DIN LINE TIED HIGH FOR FIRST TWO DUMMY CONVERSIONS

CONTROL REGISTER IS LOADED ON THE

FIRST 12 CLOCK EDGES

Figure 16. Placing into the Required Operating Mode after Supplies are Applied

–16–

REV. A

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