AD7490BCP(RevA) データシートの表示（PDF） - Analog Devices

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AD7490BCP
(Rev.:RevA)

16-Channel, 1 MSPS, 12-Bit ADC with Sequencer in 28-Lead TSSOP

Analog Devices 

AD7490

28-Lead TSSOP

PIN CONFIGURATIONS*

32-Lead LFCSP

VIN11 1

28 VIN12

VIN10 2

27 VIN13

VIN9 3

26 VIN14

NC 4

25 VIN15

VIN8 5

24 AGND

VIN7

VIN6

VIN5

6 AD7490 23 REFIN

7 TOP VIEW 22 VDD

8

(Not to Scale)

21

AGND

VIN4 9

20 CS

VIN3 10

19 DIN

VIN2 11

18 NC

VIN1 12

17 VDRIVE

VIN0 13

16 SCLK

AGND 14

15 DOUT

NC = NO CONNECT

32 31 30 29 28 27 26 25

NC 1

VIN8 2

VIN7 3

VIN6 4

VIN5 5

VIN4 6

VIN3 7

NC 8

AD7490

(NTToOtOPtPoVSVIEcIaEWlWe)

(Not to Scale)

24 VIN15

23 NC

22 AGND

21 REFIN

20 VDD

19 AGND

18 CS

17 DIN

9 10 11 12 13 14 15 16

NC = NO CONNECT

EXPOSED PAD SHOULD BE TIED TO AGND

*ALL NC PINS SHOULD BE CONNECTED STRAIGHT TO AGND

Mnemonic

CS

REFIN

VDD

AGND

VIN0–VIN15

DIN

DOUT

SCLK

VDRIVE

PIN FUNCTION DESCRIPTIONS

Function

Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the

AD7490 and also frames the serial data transfer.

Reference Input for the AD7490. An external reference must be applied to this input. The voltage range

for the external reference is 2.5 V ± 1% for specified performance.

Power Supply Input. The VDD range for the AD7490 is from 2.7 V to 5.25 V. For the 0 to 2 ϫ REFIN

range, VDD should be from 4.75 V to 5.25 V.

Analog Ground. Ground reference point for all circuitry on the AD7490. All analog/digital input signals

and any external reference signal should be referred to this AGND voltage. All AGND pins should be

connected together.

Analog Input 0 through Analog Input 15. Sixteen single-ended analog input channels that are multiplexed

into the on-chip track-and-hold. The analog input channel to be converted is selected by using the address

bits ADD3 through ADD0 of the control register. The address bits in conjunction with the SEQ and

SHADOW bits allow the Sequence Register to be programmed. The input range for all input channels can

extend from 0 V to REFIN or 0 V to 2 ϫ REFIN as selected via the RANGE bit in the Control Register.

Any unused input channels should be connected to AGND to avoid noise pickup.

Data In. Logic input. Data to be written to the AD7490’s Control Register is provided on this input and

is clocked into the register on the falling edge of SCLK (see Control Register section).

Data Out. Logic output. The conversion result from the AD7490 is provided on this output as a serial

data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream consists

of four address bits indicating which channel the conversion result corresponds to, followed by the 12 bits

of conversion data, which is provided MSB first. The output coding may be selected as straight binary or

twos complement via the CODING Bit in the Control Register.

Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock

input is also used as the clock source for the AD7490’s conversion process.

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the serial interface

of the AD7490 will operate.

–6–

REV. A

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