AD7490BRUZ-REEL データシートの表示（PDF） - Analog Devices
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AD7490BRUZ-REEL Datasheet PDF : 29 Pages
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Data Sheet
AD7490
TIMING SPECIFICATIONS
VDD = 2.7 V to 5.25 V, VDRIVE ≤ VDD, REFIN = 2.5 V; TA = TMIN to TMAX, unless otherwise noted.
Table 2. Timing Specifications1
Limit at TMIN, TMAX
Parameter VDD = 3 V VDD = 5 V
fSCLK 2
10
10
16
20
tCONVERT
16 × tSCLK
16 × tSCLK
tQUIET
50
50
t2
12
10
t33
20
14
t3b 4
30
20
t43
60
40
t5
0.4 × tSCLK 0.4 × tSCLK
t6
0.4 × tSCLK 0.4 × tSCLK
t7
15
15
t85
15/50
15/50
t9
20
20
t10
5
5
t11
20
20
t12
1
1
Unit
kHz min
MHz max
ns min
ns min
ns max
ns max
ns max
ns min
ns min
ns min
ns min/max
ns min
ns min
ns min
µs max
Description
Minimum quiet time required between bus relinquish and start of next conversion
CS to SCLK setup time
Delay from CS until DOUT three-state disabled
Delay from CS to DOUT valid
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to DOUT valid hold time
SCLK falling edge to DOUT high impedance
DIN setup time prior to SCLK falling edge
DIN hold time after SCLK falling edge
16th SCLK falling edge to CS high
Power-up time from full power-down/auto shutdown/auto standby modes
1 Guaranteed by characterization. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V (see Figure 2). The 3 V
operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.
2 The mark/space ratio for the SCLK input is 40/60 to 60/40. The maximum SCLK frequency is 16 MHz with VDD = 3 V to give a throughput of 870 kSPS. Care must be
taken when interfacing to account for data access time, t4, and the setup time required for the user’s processor. These two times determine the maximum SCLK
frequency with which the user’s system can operate (see the Serial Interface section).
3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 0.7 VDRIVE .
4 t3b represents a worst-case figure for having ADD3 available on the DOUT line, that is, if the AD7490 goes back into three-state at the end of a conversion and some
other device takes control of the bus between conversions, the user has to wait a maximum time of t3b before having ADD3 valid on the DOUT line. If the DOUT line is
weakly driven to ADD3 between conversions, the user typically has to wait 17 ns at 3 V and 12 ns at 5 V after the CS falling edge before seeing ADD3 valid on DOUT.
5 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the timing characteristics, is the true bus relinquish
time of the part and is independent of the bus loading.
200µA
IOL
TO OUTPUT
PIN CL
25pF
1.6V
200µA
IOH
Figure 2. Load Circuit for Digital Output Timing Specifications
Rev. D | Page 5 of 28
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