EVAL-AD7492CB(Rev0) データシートの表示（PDF） - Analog Devices

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EVAL-AD7492CB
(Rev.:Rev0)

1.25 MSPS, 16 mW Internal REF and CLK, 12-Bit Parallel ADC

Analog Devices 

AD7492

AD7492-5–SPECIFICATIONS1

(VDD = 4.75 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.)

Parameter

A Version1

B Version1

Unit

Test Conditions/Comments

DYNAMIC PERFORMANCE

Signal to Noise + Distortion (SINAD)

Signal-to-Noise Ratio (SNR)

Total Harmonic Distortion (THD)

Peak Harmonic or Spurious Noise (SFDR)

Intermodulation Distortion (IMD)

Second Order Terms

Third Order Terms

Aperture Delay

Aperture Jitter

Full Power Bandwidth

DC ACCURACY

Resolution

Integral Nonlinearity

Differential Nonlinearity

69

68

70

68

–83

–87

–75

–83

–90

–76

–82

–90

–71

–88

5

15

10

12

± 1.5

+1.5/–0.9

69

68

70

68

–83

–87

–75

–83

–90

–76

–82

–90

–71

–88

5

15

10

12

± 1.25

+1.5/–0.9

Offset Error

Gain Error

±9

±9

± 2.5

± 2.5

ANALOG INPUT

Input Voltage Ranges

DC Leakage Current

Input Capacitance

0 to 2.5

±1

33

0 to 2.5

±1

33

REFERENCE OUTPUT

REF OUT Output Voltage Range

2.5

2.5

LOGIC INPUTS

Input High Voltage, VINH2

Input Low Voltage, VINL2

Input Current, IIN

Input Capacitance, CIN3

LOGIC OUTPUTS

Output High Voltage, VOH

Output Low Voltage, VOL

Floating-State Leakage Current

Floating-State Output Capacitance

Output Coding

VDRIVE × 0.7

VDRIVE × 0.3

±1

10

VDRIVE × 0.7

VDRIVE × 0.3

±1

10

VDRIVE – 0.2

0.4

± 10

10

Straight (Natural) Binary

VDRIVE – 0.2

0.4

± 10

10

Straight (Natural) Binary

CONVERSION RATE

Conversion Time

680

680

Track/Hold Acquisition Time

120

120

Throughput Rate

1.25

1.25

POWER REQUIREMENTS

VDD

IDD

Normal Mode

Quiescent Current

Partial Sleep Mode

Full Sleep Mode

Power Dissipation4

Normal Mode

Partial Sleep Mode

Full Sleep Mode

4.75/5.25

3.3

1.8

250

1

16.5

1.25

5

4.75/5.25

3.3

1.8

250

1

16.5

1.25

5

NOTES

1Temperature ranges as follows: A and B Versions: –40°C to +85°C.

2VINH and VINL trigger levels are set by the VDRIVE voltage. The logic interface circuitry is powered by VDRIVE.

3Sample tested @ 25°C to ensure compliance.

4See Power vs. Throughput Rate section.

Specifications subject to change without notice.

dB typ

dB min

dB typ

dB min

dB typ

dB typ

dB max

dB typ

dB typ

dB max

dB typ

dB typ

dB typ

dB typ

ns typ

ps typ

MHz typ

Bits

LSB max

LSB max

LSB max

LSB max

V

µA max

pF typ

V

V min

V max

µA max

pF max

V min

V max

µA max

pF max

ns max

ns min

MSPS max

V min/max

mA max

mA max

µA max

µA max

mW max

mW max

µW max

fS = 1.25 MSPS

fIN = 500 kHz Sine Wave

fIN = 100 kHz Sine Wave

fIN = 500 kHz Sine Wave

fIN = 100 kHz Sine Wave

fIN = 500 kHz Sine Wave

fIN = 100 kHz Sine Wave

fIN = 100 kHz Sine Wave

fIN = 500 kHz Sine Wave

fIN = 100 kHz Sine Wave

fIN = 100 kHz Sine Wave

fIN = 500 kHz Sine Wave

fIN = 100 kHz Sine Wave

fIN = 500 kHz Sine Wave

fIN = 100 kHz Sine Wave

fS = 1.25 MSPS

Guaranteed No Missed Codes to

12 Bits (A and B Version)

± 1.5% for Specified Performance

VDD = 5 V ± 5%

VDD = 5 V ± 5%

Typically 10 nA, VIN = 0 V or VDD

ISOURCE = 200 µA

ISINK = 200 µA

Conversion Time + Acquisition Time

Digital I/Ps = 0 V or DVDD.

fS = 1.25 MSPS, Typ 2.75 mA

Static. Typ 190 µA

Static. Typ 200 nA

Digital I/Ps = 0 V or DVDD

–2–

REV. 0

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