EVAL-AD7492CB(Rev0) データシートの表示（PDF） - Analog Devices
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EVAL-AD7492CB Datasheet PDF : 16 Pages
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AD7492–SPECIFICATIONS1
(VDD = 2.7 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.)
AD7492
Parameter
A Version1
B Version1
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
fS = 1 MSPS
Signal to Noise + Distortion (SINAD)
69
69
dB typ
fIN = 500 kHz Sine Wave
68
68
dB min
fIN = 100 kHz Sine Wave
Signal-to-Noise Ratio (SNR)
70
70
dB typ
fIN = 500 kHz Sine Wave
68
68
dB min
fIN = 100 kHz Sine Wave
Total Harmonic Distortion (THD)
–85
–85
dB typ
fIN = 500 kHz Sine Wave
–87
–87
dB typ
fIN = 100 kHz Sine Wave
–75
–75
dB max
fIN = 100 kHz Sine Wave
Peak Harmonic or Spurious Noise (SFDR) –86
–86
dB typ
fIN = 500 kHz Sine Wave
–90
–90
dB typ
fIN = 100 kHz Sine Wave
–76
–76
dB max
fIN = 100 kHz Sine Wave
Intermodulation Distortion (IMD)
Second Order Terms
–77
–77
dB typ
fIN = 500 kHz Sine Wave
–90
–90
dB typ
fIN = 100 kHz Sine Wave
Third Order Terms
–69
–69
dB typ
fIN = 500 kHz Sine Wave
–88
–88
dB typ
fIN = 100 kHz Sine Wave
Aperture Delay
5
5
ns typ
Aperture Jitter
15
15
ps typ
Full Power Bandwidth
10
10
MHz typ
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
12
± 1.5
+1.5/–0.9
±9
± 2.5
12
± 0.6
±1
+1.5/–0.9
±9
± 2.5
Bits
LSB max
LSB typ
LSB max
LSB max
LSB max
LSB max
fS = 1 MSPS
VDD = 5 V
VDD = 3 V
Guaranteed No Missed Codes to
12 Bits (A and B Version)
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
0 to 2.5
±1
33
0 to 2.5
±1
33
V
µA max
pF typ
REFERENCE OUTPUT
REF OUT Output Voltage Range
2.5
2.5
V
± 1.5% for Specified Performance
LOGIC INPUTS
Input High Voltage, VINH2
Input Low Voltage, VINL2
Input Current, IIN
Input Capacitance, CIN3
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance
Output Coding
VDRIVE × 0.7
VDRIVE × 0.3
±1
10
VDRIVE × 0.7
VDRIVE × 0.3
±1
10
V min
V max
µA max
pF max
VDRIVE – 0.2
0.4
± 10
10
Straight (Natural) Binary
VDRIVE – 0.2
0.4
± 10
10
Straight (Natural) Binary
V min
V max
µA max
pF max
VDD = 5 V ± 5%
VDD = 5 V ± 5%
Typically 10 nA, VIN = 0 V or VDD
ISOURCE = 200 µA
ISINK = 200 µA
CONVERSION RATE
Conversion Time
880
880
ns max
Track/Hold Acquisition Time
120
120
ns min
Throughput Rate
1
1
MSPS max Conversion Time + Acquisition Time
POWER REQUIREMENTS
VDD
IDD
Normal Mode
Quiescent Current
Partial Sleep Mode
Full Sleep Mode
Power Dissipation4
Normal Mode
Partial Sleep Mode
Full Sleep Mode
2.7/5.25
3
1.8
250
1
15
1.25
5
2.7/5.25
3
1.8
250
1
15
1.25
5
NOTES
1Temperature ranges as follows: A and B Versions: –40°C to +85°C.
2VINH and VINL trigger levels are set by the VDRIVE voltage. The logic interface circuitry is powered by VDRIVE.
3Sample tested @ 25°C to ensure compliance.
4See Power vs. Throughput Rate section.
Specifications subject to change without notice.
V min/max
mA max
mA max
µA max
µA max
mW max
mW max
µW max
Digital I/Ps = 0 V or DVDD.
fS = 1 MSPS, Typ 2.2 mA
Static. Typ 190 µA
Static. Typ 200 nA
Digital I/Ps = 0 V or DVDD
VDD = 5 V
VDD = 5 V
VDD = 5 V
REV. 0
–3–
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